S-8233C Datasheet, PDF (13/26 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK

Rev.4.0_00
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233C Series
Over discharge condition
If any one of the battery voltages falls below the over discharge detection voltage (V_DD) during discharging
under normal condition and it continues for the over discharge detection delay time (t_DD) or longer, the
discharging FET turns off and discharging stops. This condition is called the over discharge condition. In
this condition, output voltage of DSO goes ‘High’. When the discharging FET turns off, the VMP terminal
voltage becomes equal to the V_SS voltage and the IC's current consumption falls below the power-down
current consumption (I_PDN). This condition is called the power-down condition. The VMP and VSS
terminals are shorted by the R_VSM resistor under the over discharge and power-down conditions.
The power-down condition is canceled when the charger is connected and the voltage between VMP and
VSS is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes equal to
or higher than the over discharge release voltage (V_DU) in this condition, the over discharge condition
changes to the normal condition. In this condition, output voltage of DSO goes ‘Low’.
Delay circuits
The over charge detection delay time (t_CU1 to t_CU3), over discharge detection delay time (t_DD1 to t_DD3), and
over current detection delay time 1 (t_IOV1) are changed with external capacitors (C4 to C6).
The delay times are calculated by the following equations:
Min. Typ. Max.
t_CU[s] =Delay factor ( 1.07, 2.13, 3.19)×C4 [uF]
t_DD[s] =Delay factor ( 0.20, 0.40, 0.60)×C5 [uF]
t_IOV1[s]=Delay factor ( 0.10, 0.20, 0.30)×C6 [uF]
Caution The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The
delay time cannot be changed via an external capacitor.
CTL terminal
If the CTL terminal is floated under normal condition, it is pulled up to the V_CC potential in the IC, and both
the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and
discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time,
the VMP and VCC terminals are shorted by the R_VCM resistor.
When the CTL terminal becomes equal to V_SS potential, charging and discharging are enabled and go
back to their appropriate conditions for the battery voltages.
Caution Please note unexpected behavior might occur when electrical potential difference
between the CTL pin ('L' level) and VSS is generated through the external filter
(R_VSS and C_VSS) as a result of input voltage fluctuations.
0 V battery charging function
This function is used to recharge the three serially-connected batteries after they self-discharge to 0 V.
When the 0 V charging start voltage (V_0CHAR) or higher is applied to between VMP and VSS by connecting
the charger, the charging FET gate is fixed to V_SS potential.
When the voltage between the gate sources of the charging FET becomes equal to or higher than the
turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the
discharging FET turns off and the charging current flows through the internal parasitic diode in the
discharging FET. If all the battery voltages become equal to or higher than the over discharge release
voltage (V_DU), the normal condition returns.
CAUTION In the products without 0 V battery charging function, the resistance between VCC and
VMP and between VSS and VMP are lower than the products with 0 V battery charging
function. It causes to that over charge detection voltage increases by the drop voltage
of R5 (see Figure 8 for a connection example) with sink current at VMP.
The COP output is undefined below 2.0 V on VCC-VSS voltage in the products without
0 V battery charging function.
Seiko Instruments Inc.
13