S-1200 Datasheet, PDF (13/31 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT LOW INPUT-AND-OUTPUT CAPACITANCE CMOS VOLTAGE REGULATOR

HIGH RIPPLE-REJECTION LOW DROPOUT LOW INPUT-AND-OUTPUT CAPACITANCE CMOS VOLTAGE REGULATOR
Rev.3.2_00
S-1200 Series
„ Operation
1. Basic operation
Figure 12 shows the block diagram of the S-1200 Series.
The error amplifier compares the reference voltage (V_ref) with V_fb, which is the output voltage resistance-
divided by feedback resistors R_s and R_f. It supplies the output transistor with the gate voltage necessary
to ensure a certain output voltage free of any fluctuations of input voltage and temperature.
VIN
Current
supply
V_ref
Error
amplifier
−
+
Reference voltage
circuit
*1
R_f
V_fb
R_s
VOUT
VSS
*1.
Parasitic diode
Figure 12
2. Output transistor
The S-1200 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that V_OUT does not exceed V_IN + 0.3 V to prevent the voltage regulator from being damaged due
to inverse current flowing from the VOUT pin through a parasitic diode to the VIN pin.
Seiko Instruments Inc.
13