S814 Datasheet, PDF (12/32 Pages) Seiko Instruments Inc – LOW DROPOUT CMOS VOLTAGE REGULATOR

LOW DROPOUT CMOS VOLTAGE REGULATOR
S-814 Series
Rev.3.1_00
 Operation
1. Basic operation
Figure 12 shows the block diagram of the S-814 Series.
The error amplifier compares the reference voltage (V_ref) with feedback voltage (V_fb), which is the output
voltage resistance-divided by feedback resistors (R_s and R_f). It supplies the gate voltage necessary to
maintain the constant output voltage which is not influenced by the input voltage and temperature
change, to the output transistor.
VIN
Current
supply
V_ref
Error
amplifier
−
+
Reference voltage
circuit
*1
R_f
V_fb
R_s
VOUT
VSS
*1. Parasitic diode
Figure 12
2. Output transistor
In the S-814 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that V_OUT does not exceed V_IN+0.3 V to prevent the voltage regulator from being damaged due to
reverse current flowing from VOUT pin through a parasitic diode to VIN pin, when the potential of V_OUT
became higher than V_IN.
12
Seiko Instruments Inc.