S-5742NBL0I-Y3N2U Datasheet, PDF (12/21 Pages) Seiko Instruments Inc – HIGH-WITHSTAND VOLTAGE HIGH-SPEED

HIGH-WITHSTAND VOLTAGE HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5742 I Series
Rev.2.1_00
4. Timing chart
Figure 15 shows the operation timing at power-on.
The initial output voltage at rising of power supply voltage (V_DD) is either "H" or "L".
In case of B > B_OP (operation point) or B < B_RP (release point) at the time when the start up time (t_PON) is passed after
rising of V_DD, this IC outputs V_OUT according to the applied magnetic flux density.
In case of B_RP < B < B_OP at the time when t_PON is passed after rising of V_DD, this IC maintains the initial output voltage.
Product with V_OUT = "L" at S pole detection
Product with V_OUT = "H" at S pole detection
Power supply voltage
(VDD)
tPON
Power supply voltage
(VDD)
tPON
Output voltage (VOUT)
(B > BOP)
"H" / "L"
"L"
Output voltage (VOUT)
(B > BOP)
"H" / "L"
"H"
Output voltage (VOUT)
(B < BRP)
"H" / "L"
Output voltage (VOUT)
(BRP < B < BOP)
"H" / "L"
"H"
Output voltage (VOUT)
(B < BRP)
"H" / "L"
Latching
Output voltage (VOUT)
(BRP < B < BOP)
Figure 15
"H" / "L"
"L"
Latching
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