S-8204BAB-TCT1Y Datasheet, PDF (11/36 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC

Rev.3.9_00
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
3. 7 CIT pin detection voltage (V_CIT)
The CIT pin detection voltage (V_CIT) is the voltage at the CIT pin when the DOP pin's voltage is set to "L" (voltage
V_DS × 0.1 V or less) after increasing the CIT pin's voltage gradually, after setting V_VINI = V_DIOV1 max. + 0.05 V from
the initial status.
3. 8 Load short-circuit detection delay time (t_SHORT)
Load short-circuit detection delay time (t_SHORT) is a period in which the VINI pin's voltage changes from "H" to "L"
by changing the VINI pin's voltage instantaneously from the initial status to V_SHORT max. + 0.05 V.
4. 0 V battery charge starting voltage (0 V battery charge function "available"), 0 V battery charge
inhibition battery voltage (0 V battery charge function "unavailable")
(Test circuit 2)
Confirm both COP pin and DOP pin are in "H" (its voltage level is V_DS × 0.9 V or more) after setting V_VMP = V_SEL =
V_CTLC = V_CTLD = V_DD, V_VINI = V_SS, CCT pin = Open, CDT pin = Open, CIT pin = Open, V1 = V2 = V3 = V4 = 3.5 V.
(This status is referred to as initial status.)
According to user's selection of the function to charge 0 V battery, either function of voltage for start charging 0 V
battery or battery voltage for inhibit charging 0 V battery is applied to each product.
4. 1 0 V battery charge starting voltage (V_0CHA) (0 V battery charge function "available")
0 V battery charge starting voltage (V_0CHA) is a voltage at V1; when a voltage at the COP pin is set to "H" after
increasing a voltage at V1 gradually, after setting V1 = V2 = V3 = V4 = 0 V from the initial status.
4. 2 0 V battery charge inhibition battery voltage (V_0INH) (0 V battery charge function "unavailable")
0 V battery charge inhibition battery voltage (V_0INH) is a voltage at V1; when a voltage at the COP pin is set to "L"
after decreasing a voltage at V1 gradually from the initial status.
5. Resistance between VMP pin and VDD pin, resistance between VMP pin and VSS pin, VC1 pin
current, VC2 pin current, VC3 pin current, VC4 pin current, CTLC pin current "H", CTLC pin
current "L", CTLD pin current "H", CTLD pin current "L", SEL pin current "H", SEL pin current
"L", COP pin source current, COP pin leakage current, DOP pin source current, DOP pin sink
current
(Test circuit 4)
Set V_CTLC = V_CTLD = V_VMP = V_SEL = V_DD, V_VINI = V_SS, V1 = V2 = V3 = V4 = 3.5 V, set other pins open. (This status is
referred to as initial status.)
5. 1 Resistance between VMP pin and VDD pin (R_VMD)
The value of resistance between VMP pin and VDD pin (R_VMD) can be defined by R_VMD = V_DS / I_VMD by using the
VMP pin's current (I_VMD) when V_VINI = 1.5 V and V_VMP = V_SS after the initial status.
5. 2 Resistance between VMP pin and VSS pin (R_VMS)
The value of resistance between VMP pin and VSS pin (R_VMS) can be defined by R_VMS = V_DS / I_VMS by using the
VMP pin's current (I_VMS) when V1 = V2 = V3 = V4 = 1.8 V after the initial status.
5. 3 VC1 pin current (I_VC1), VC2 pin current (I_VC2), VC3 pin current (I_VC3), VC4 pin current (I_VC4)
In the initial status, each current flows in the VC1 pin, VC2 pin, VC3 pin, VC4 pin is the VC1 pin current (I_VC1), the
VC2 pin current (I_VC2), the VC3 pin current (I_VC3), the VC4 pin current (I_VC4), respectively.
5. 4 CTLC pin current "H" (I_CTLCH), CTLC pin current "L" (I_CTLCL)
In the initial status, a current which flows in the CTLC pin is the CTLC pin current "H" (I_CTLCH). After that,
decreasing a voltage at the CTLC pin gradually, the maximum current which flows in the CTLC pin is; the CTLC
pin current "L" (I_CTLCL).
11