S-24C04BPHAL Datasheet, PDF (11/38 Pages) Seiko Instruments Inc – 2-WIRE CMOS SERIAL E2PROM

Rev.2.1_00
2-WIRE CMOS SERIAL E²PROM
S-24C04BPHAL
5. Device addressing
To perform data communications, the master device mounted on the system outputs the start condition signal
to the slave device. Next, the master device outputs a 7-bit device address and a 1-bit read/write instruction
code onto the SDA bus.
The higher 4 bits of the device address are called the “Device Code”, and are fixed to “1010”. The following 2
bits are “don’t care” bits.
When the comparison results match, the slave device outputs the acknowledge signal during the 9th clock
cycle.
Device code
Don’t
care
Page
address
S-24C04BPHAL 1
0
1
0
X
X
P0 R / W
MSB
LSB
Remark X: Don’t care
Figure 9 Device Address
In the S-24C04BPHAL, the 7th bit is a page address bit.
Accordingly, when P0 = 0, the first half of the memory area (2 Kb: addresses 000h to 0FFh) is selected; when
P0 = 1, the second half of the memory area (2 Kb; addresses 100h to 1FFh) are selected.
Seiko Instruments Inc.
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