S-1112_1 Datasheet, PDF (11/30 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR

HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.1_00
S-1112/1122 Series
„ Standard Circuit
Input
C_IN^*1
VIN VOUT
ON/OFF
VSS
Output
C_L^*2
Single GND
GND
*1. C_IN is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 0.47 µF or more can be used for C_L.
Figure 10
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
„ Application Conditions
Input capacitor (C_IN):
Output capacitor (C_L):
ESR of output capacitor:
1.0 µF or more
0.47 µF or more
10 Ω or less
Caution A general series regulator may oscillate, depending on the external components selected.
Check that no oscillation occurs with the application using the above capacitor.
Seiko Instruments Inc.
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