S-8233B_1 Datasheet, PDF (10/26 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK

BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233B Series
Rev.4.2_00
(13) Measurement 13 Measurement circuit 8
Set S4 to ON, S1, S2, S3, S5, and S6 to OFF, V1, V2, V3 to 3.5 V and V6, V7, and V8 to 0 V under
normal condition. Increase V5 from 0 V gradually. The V5 voltage when I5 = 10 μA is the CD1'L' voltage
(V_CD1(L))
Set S5 to ON, S1, S2, S3, S4, and S6 to OFF, V1, V2, and V3 to 3.5 V and V5, V7, and V8 to 0 V under
normal condition. Increase V6 from 0 V gradually. The V6 voltage when I6 = 10 μA is the CD2'L' voltage
(V_CD2(L)).
Set S6 to ON, S1, S2, S3, S4, and S5 to OFF, V1, V2, and V3 to 3.5 V and V5, V6, and V8 to 0 V under
normal condition. Increase V7 from 0 V gradually. The V7 voltage when I7 = 10 μA is the CD3'L' voltage
(V_CD3(L)).
Set S1 to ON, S2, S3, S4, S5, and S6 to OFF, V1 to 4.5 V, V2 and V3 to 3.5 V and V5, V6, and V7 to 0 V
under over charge condition. Increase V8 from 0 V gradually. The V8 voltage when I8 = 0.1 μA is the
CD1'H' voltage (V_CD1(H)).
Set S2 to ON, S1, S3, S4, S5, and S6 to OFF, V2 to 4.5 V, V1 and V3 to 3.5 V and V5, V6, and V7 to 0 V
under over charge condition. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 μA is the
CD2'H' voltage (V_CD2(H)).
Set S3 to ON, S1, S2, S4, S5, and S6 to OFF, V3 to 4.5 V, V1 and V2 to 3.5 V and V5, V6, and V7 to 0 V
under over charge condition. Increase V8 from 0 V gradually. The V8 voltage when I8 = 0.1 μA is the
CD3'H' voltage (V_CD3(H)).
(14) Measurement 14 Measurement circuit 9
Set V1, V2, and V3 to 4.5 V under over charge condition. The current I1 flowing to COP terminal is COP
OFF LEAK current (I_COL).
(15) Measurement 15 Measurement circuit 10
Set V1, V2, and V3 to 0 V, and V5 to 2 V, and decrease V5 gradually. The V5 voltage when COP = 'H'
(V_SS + 0.3 V or higher) is the 0 V charge start voltage (V_0CHAR).
(16) Measurement 16 Measurement circuit 1 ( Measurement will be changed by the CTL logic! )
1) If the CTL logic is “normal”
Set V1, V2, and V3 to 3.5 V, and V4 to 0 V, and increase V4 gradually. The V4 voltage when COP
= 'H' (V_SS + 0.3 V or higher) and DOP = 'H' (V_SS + 0.3 V or higher) is the CTL 'H' input voltage
(V_CTL(H))_.
After that decrease V4 gradually. The V4 voltage when COP = 'L' (V_CC - 0.3 V or lower) and DOP =
'L' (V_CC - 0.3 V or lower) is the CTL'L' input voltage (V_CTL(L)).
2) If the CTL logic is “reverse”
Set V1, V2, and V3 to 3.5 V, and V4 to10.5 V, and decrease V4 gradually. The V4 voltage when
COP = 'H' (V_SS + 0.3 V or higher) and DOP = 'H' (V_SS + 0.3 V or higher) is the CTL'L' input voltage
(V_CTL(L)).
After that increase V4 gradually. The V4 voltage when COP ='L' (V_VMP - 0.3 V or lower) and DOP
= 'L' (V_CC - 0.3 V or lower) is the CTL'H' input voltage (V_CTL(H)).
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