S-25A256B Datasheet, PDF (10/23 Pages) Seiko Instruments Inc – Function to prevent malfunction by monitoring clock pulse

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E²PROM
S-25A256B
 Instruction Set
Rev.1.2_01
Table 15 is the list of instruction for This IC. the instruction is able to be input by changing the CS pin "H" to "L". Input
the instruction in the MSB first. Each instruction code is organized with 1-byte as shown below. If this IC receives any
invalid instruction code, this IC goes in the non-select status.
Table 15 Instruction Set
Instruction Code
Address
Instruction
Operation
SCK Input Clock SCK Input Clock SCK Input Clock
1 to 8
9 to 16
17 to 24
WREN
Write enable
0000 0110
－
－
WRDI
Write disable
0000 0100
－
－
RDSR
Read the status
register
0000 0101
b7 to b0 output^*1
－
WRSR
Write in the status
register
0000 0001
b7 to b0 input
－
READ
Read memory data
0000 0011
A15 to A8^*2
A7 to A0
WRITE
Write memory data
0000 0010
A15 to A8^*2
A7 to A0
*1. Sequential data reading is possible.
*2. The higher addresses A15 = Don't care.
*3. After outputting data in the specified address, data in the following address is output.
Data
SCK Input Clock
25 to 32
－
－
－
－
D7 to D0 output^*3
D7 to D0 input
 Operation
1. Status register
The status register's organization is below. The status register can write and read by a specific instruction.
b7
b6
b5
b4
b3
b2
b1
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Disable
Block Protect
Write Enable Latch
Write In Progress
Figure 8 Organization of Status Register
The status / control bits of the status register as follows.
1. 1 SRWD (b7) : Status Register Write Disable
Bit SRWD operates in conjunction with the write protect signal ( WP ). With a combination of bit SRWD and signal
WP (SRWD = "1", WP = "L"), this IC goes in Hardware Protect status. In this case, the bits composed of the
nonvolatile memory in the status register (SRWD, BP1, BP0) go in read only, so that the WRSR instruction is not
be performed.
10