SLX24C164P Datasheet, PDF(9/27 Page) Siemens Semiconductor Group – 16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection Mode

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SLX24C164P Datasheet, PDF (9/27 Pages) Siemens Semiconductor Group – 16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection Mode

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SLx 24C164/P

Device Addressing and EEPROM Addressing

After a START condition, the master always transmits a Command Byte CSW or CSR.

After the acknowledge of the EEPROM a Control Byte follows, its content and the

transmitter depend on the previous Command Byte. The description of the Command

and Control Bytes is shown in table 2.

Command Byte

Control Byte

Selects one of the 8 addressable devices: the chip select bits c2,

c1 and c0 (bit positions b6 to b4) are compared to their

corresponding hard wired input pins CS2, CS1 and CS0,

respectively (c1 is the complement of CS1 pin).

Selects operation: the least significant bit b0 is low for a write

operation (Chip Select Write Command Byte CSW) or set high for a

read operation (Chip Select Read Command Byte CSR).

Contains address information: in the CSW Command Byte, the

bit positions b3 to b1 are decoded for the three uppermost EEPROM

address bits A10, A9, A8 (in the CSR Command Byte, the bit

positions b3 to b1 are left undefined).

Following CSW (b0 = 0): contains the eight lower bits of the

EEPROM address (EEA) bit A7 to A0, or an additional command

byte for the handling of the protection bit.

Following CSR (b0 = 1): contains the data read out, transmitted by

the EEPROM. The EEPROM data are read as long as the master

pulls down SDA after each byte in order to acknowledge the

transfer. The read operation is stopped by the master by releasing

SDA (no acknowledge is applied) followed by a STOP condition.

Table 2

Command and Control Byte for I2C-Bus Addressing of Chip and EEPROM

CSW

CSR

EEA

Definition

Function

b7 b6 b5 b4 b3 b2 b1 b0

1 c2 c1 c0 A10 A9 A8 0 Chip Select for Write

1 c2 c1 c0 x x x 1 Chip Select for Read

A7 A6 A5 A4 A3 A2 A1 A0 EEPROM address

The device has an internal address counter which points to the current EEPROM

address.

The address counter is incremented

â after a data byte to be written has been acknowledged, during entry of further data

byte

â during a byte read, thus the address counter points to the following address after

reading a data byte.

Semiconductor Group

1998-07-27

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