SDA5642-6 Datasheet, PDF (9/27 Pages) Siemens Semiconductor Group – VPS-Decoder

SDA 5642-6/X
2.2 I²C Bus
2.2.1 General Information
The I²C-Bus interface implemented on the VPS decoder is a slave transmitter/receiver,
i.e., both reading from and writing to the VPS decoder is possible. The clock line SCL is
controlled only by the bus master usually being a micro controller, whereas the SDA line
is controlled either by the master or by the slave. A data transfer can only be initiated by
the bus master when the bus is free, i.e., both SDA and SCL lines are in a high state. As
a general rule for the I²C Bus, the SDA line changes state only when the SCL line is low.
The only exception to that rule are the Start Condition and the Stop Condition. Further
Details are given below. The following abbreviations are used:
START:
AS:
AM:
NAM:
STOP:
Start Condition generated by master
Acknowledge by slave
Acknowledge by master
No Acknowledge by master
Stop condition generated by master
2.2.2 Chip Address
There are two pairs of chip addresses, which are selected by the CS0-input pin
according to the following table:
CS0 Input
Low
High
Write Mode
20 (hex)
22 (hex)
Read Mode
21 (hex)
23 (hex)
Semiconductor Group
9
02.97