SDA5642-6 Datasheet, PDF (8/27 Pages) Siemens Semiconductor Group – VPS-Decoder

SDA 5642-6/X
2
System Description
2.1 Functions
Referring to the functional block diagram of the VPS decoder, the composite video signal
with negative going sync pulses is coupled to the pin CVBS through a capacitor which is
used for clamping the bottom of the sync pulses to an internally fixed level. The signal is
passed on to the slicer, an analogue circuitry separating the sync and the data parts of
the CVBS signal, thus yielding the digital composite sync signal VCS and a digital data
signal for further processing by comparing those signals to internally generated slicing
levels.
The output of the sync separator is forwarded, on one hand, to the output pin VCS, and
on the other hand, to the clock generator and the timing block. The VCS signal
represents a key signal that is used for deriving a system clock signal by means of a PLL
and all other timing signal.
The data slicer separates the data signal from the CVBS signal by comparing the video
voltage to an internally generated slicing level which is found by averaging the data
signal during TV line no. 16.
The clock generator delivers the system clock needed for the basic timing as well as for
the regeneraton of the dataclock. It is based on two phase locked loops (PLL’s) all parts
of which are integrated on chip with the exception of the loop filter components. Each of
the PLL’s is composed of a voltage controlled relaxation oscillator (VCO), a phase/
frequency detector (PFD), and a charge pump which converts the digital output signals
of the PFD to an analogue current. That current is transformed to a control voltage for
the VCO by the off-chip loop filter. The generated VCO frequency is 10 MHz.
All signals necessary for the control of sync and data slicing as well as for the data
acquisition are generated by the Timing block.
The extracted data bits of TV line no. 16 are checked for biphase errors. With no biphase
errors encountered, the acquired bytes are stored in the transfer register to the I²C Bus.
That transfer is signalled by a H/L transition of the DAVN output.
Data are updated when a new data line has been received, provided that the chip is not
accessed via the I²C Bus at the same time.
A micro controller can read the stored bytes via the I²C-Bus interface at any time.
However, one must be aware that the storage of new data from the acquisition interface
is inhibited as long as the VPS decoder is being accessed via the I²C Bus.
Semiconductor Group
8
02.97