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PEB2054 Datasheet, PDF (81/269 Pages) Siemens Semiconductor Group – ICs for Communications | |||
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PSB
PTL
COS
MFPS
CSB
RBS
PEB 2055
PEF 2055
Detailed Register Description
PCM Standby.
0â¦the PCM interface output pins TxD0..3 are set to high impedance and
those TSC pins that are actually used as tristate control signals are set
to logical 1 (inactive).
1â¦the PCM output pins transmit the contents of the upstream data memory
or may be set to high impedance via the data memory tristate field.
PCM Test Loop.
0â¦the PCM test loop is disabled.
1â¦the PCM test loop is enabled, i.e. the physical transmit pins TxD# are
internally connected to the corresponding physical receive pins RxD#,
such that data transmitted over TxD# are internally looped back to RxD#
and data externally received over RxD# are ignored. The TxD# pins still
output the contents of the upstream data memory according to the setting
of the tristate field (only modes 0 and 1; mode 1 with AIS bit set).
CFI Output driver Selection.
0â¦the CFI output drivers are tristate drivers.
1â¦the CFI output drivers are open drain drivers.
Monitor/Feature control channel Protocol Selection.
0â¦handshake facility disabled (SLD and IOM-1 applications)
1â¦handshake facility enabled (IOM-2 applications)
CFI Standby.
0â¦the CFI interface output pins DD0..3, DU0..3, DCL and FSC are set to
high impedance.
1â¦the CFI output pins are active.
Register Bank Selection. Used in demultiplexed data/address modes only.
0â¦to access the registers used during device operation
1â¦to access the registers used during device initialization.
Semiconductor Group
81
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