PEB2054 Datasheet, PDF (227/269 Pages) Siemens Semiconductor Group – ICs for Communications

PEB 2055
PEF 2055
Application Hints
The following register bits are used in conjunction with the PCM framing supervision:
Interrupt Status Register
read/write reset value:
00_H
bit 7
bit 0
ISTA:
TIN
SFI MFFI MAC PFI
PIM
SIN SOV
The ISTA register should be read after an interrupt in order to determine the interrupt
source. In connection with the PCM framing control one maskable (MASK) interrupt bit
is provided by the EPIC:
PFI:
PCM Framing Interrupt; if this bit is set to logical 1, the STAR:PSS bit
has changed its polarity. To determine whether the PCM interface is
synchronized or not, STAR must be read. The PFI bit is reset by
reading ISTA.
Status Register
STAR:
bit 7
MAC
TAC
PSS
read
reset value:
05_H
bit 0
MFTO MFAB MFAE MFRW MFFE
The STAR register bits do not generate interrupts and are not modified by reading
STAR. However, each change of the PSS bit (0 → 1 and 1 → 0) causes an ISTA:PFI
interrupt.
PSS:
PCM Synchronization Status; while the PCM interface is
synchronized, the PSS bit is set to logical 1. The PSS bit is reset to
logical 0 if there is a mismatch between the PBNR value and the
applied clock and framing signals (PDC/PFS) or if OMDR:OMS0 = 0.
5.8.4 Power and Clock Supply Supervision/Chip Version
Power and Clock Supply Supervision
The + 5 V power supply line (V_DD) and the reference clock (RCL) are continuously
checked by the EPIC for spikes that may disturb the proper operation of the EPIC. If such
an inappropriate clocking or power failure occurs, data in the internal memories may be
lost, and a reinitialization of the EPIC is necessary. An Initialization Request status bit
(VNSR:IR) can be interrogated periodically by the µP to determine the current status of
the device.
In normal chip operation, the IR bit should never be set, not even after power on or when
the clock signals are switched on and off. The IR bit will only be set if spikes (< 10 ns)
are detected on the clock and power lines which may affect the data transfer on the EPIC
internal buses.
Semiconductor Group
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