C167CR-16RM Datasheet, PDF (46/67 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

C167CR-16RM _{20Dec96@09:25h Intermediate Version}
AC Characteristics
Definition of Internal Timing
The internal operation of the C167CR-16RM is controlled by the internal CPU clock f_CPU. Both
edges of the CPU clock can trigger internal (eg. pipeline) or external (eg. bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time between
two consecutive edges of the CPU clock, called “TCL” (see figure below).
Phase Locked Loop Operation
f_XTAL
f_CPU
Direct Clock Drive
f_XTAL
f_CPU
Figure 11
Generation Mechanisms for the CPU Clock
AAA_TCLAAA_TCLAAA
AAAA_TCLAAAA_TCLAAAA
The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their
variation (and also the derived external timing) depends on the used mechanism to generate f_CPU.
This influence must be regarded when calculating the timings for the C167CR-16RM.
Direct Drive
When pin P0.15 (P0H.7) is low (‘0’) during reset the on-chip phase locked loop is disabled and the
CPU clock is directly driven from the internal oscillator with the input clock signal.
The frequency of f_CPU directly follows the frequency of f_XTAL so the high and low time of f_CPU (ie. the
duration of an individual TCL) is defined by the duty cycle of the input clock f_XTAL.
The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL
that is possible under the respective circumstances. This minimum value can be calculated via the
following formula:
TCL_min = 1/f_XTAL * DC_min
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of f_XTAL is compensated so the
duration of 2TCL is always 1/f_XTAL. The minimum value TCL_min therefore has to be used only once
for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of
TCLs (2,4,...) may use the formula 2TCL = 1/f_XTAL.
Note: The address float timings in Multiplexed bus mode (t₁₁ and t₄₅) use the maximum duration of
TCL (TCL_max = 1/f_XTAL * DC_max) instead of TCL_min.
Semiconductor Group
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