C167CR-16RM Datasheet, PDF (20/67 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

C167CR-16RM _{20Dec96@09:25h Intermediate Version}
The C167CR-16RM also provides an excellent mechanism to identify and to process exceptions or
error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause
immediate non-maskable system reaction which is similar to a standard interrupt service (branching
to a dedicated vector table location). The occurence of a hardware trap is additionally signified by
an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service
is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise during run-
time:
Exception Condition
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
Protected Instruction
Fault
Illegal Word Operand
Access
Illegal Instruction Access
Illegal External Bus
Access
Reserved
Software Traps
TRAP Instruction
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
RESET 00’0000_H 00_H
III
RESET 00’0000_H 00_H
III
RESET 00’0000_H 00_H
III
NMI
NMITRAP 00’0008_H 02_H
II
STKOF STOTRAP 00’0010_H 04_H
II
STKUF STUTRAP 00’0018_H 06_H
II
UNDOPC BTRAP 00’0028_H 0A_H
I
PRTFLT BTRAP 00’0028_H 0A_H
I
ILLOPA BTRAP 00’0028_H 0A_H
I
ILLINA
BTRAP 00’0028_H 0A_H
I
ILLBUS BTRAP 00’0028_H 0A_H
I
[2C_H – 3C_H]
Any
[00’0000_H –
00’01FC_H]
in steps
of 4_H
[0B_H – 0F_H]
Any
[00_H – 7F_H]
Current
CPU
Priority
Semiconductor Group
18