SDA3302 Datasheet, PDF (4/27 Pages) Siemens Semiconductor Group – GHz PLL with I2C Bus and Four Chip Addresses

SDA 3302 Family
Circuit Description (cont’d)
Logic Allocations
Address byte
MSB
A = Acknowledge
1
1
0
0
0 MA1 MA0 0
A
Prog. divider byte 1
0 n14 n13 n12 n11 n10 n9 n8 A
Prog. divider byte 2 n7 n6 n5 n4 n3 n2 n1 n0 A
Control info. byte 1
1 5I T1 T0 1
1
1 OS A
Control info. byte 2
P7 P6 P5 P4 X P2 P1 P0 A
Divider Ratio
N = 16384 × n14 + 8192 × n13 + 4096 × n12 + 2048 × n11 + 1024 × n10 + 512 × n9 + 256 × n8 +
+ 128 × n7 + 64 × n6 + 32 × n5 + 16 × n4 + 8 × n3 + 4 × n2 + 2 × n1
+ n0
Band Selection
P2-P0 = 1
Open-collector output is active.
Port Outputs
P7-P4 = 1
Open-collector output is active.
Pump Current Switchover
5I = 1
High current.
UD Disable
OS = 1
V_D is disabled.
Test Mode
T1, T0 = 0,0
T1 = 1
T0 = 1
Normal mode
P6 = f_REF; P7 = Cy
Tristate charge pump PD is in high-impedance.
Semiconductor Group
4