SDA3302 Datasheet, PDF (2/27 Pages) Siemens Semiconductor Group – GHz PLL with I2C Bus and Four Chip Addresses

SDA 3302 Family
Functional Description
Combined with a VCO (tuner) the SDA 3302 device, with four hardware-switched chip
addresses, forms a digitally programmable phase-locked loop for use in television sets with
PLL frequency-synthesis tuning.
The PLL permits precise crystal-controlled setting of the frequency of the tuner oscillators
between 16 and 1300 MHz in increments of 62.5 kHz. The tuning process is controlled by a
microprocessor via an I²C bus. The crystal oscillator generates a sinusoidal signal suppressing
the higher-order harmonics, which reduces the moiré noise considerably.
Circuit Description
Tuning Section (refer to block diagram)
UHF/VHF
REF
Q1, Q2
The tuner signal is capacitively coupled at the UHF/VHF input and
subsequently amplified. The reference input REF should be decoupled to
ground using a capacitor of low series inductance. The signal passes
through an asynchronous divider with a fixed ratio of P = 8, an adjustable
divider with ratio N = 256 through 32767 and is then compared in a digital
phase/frequency detector to a reference frequency f_REF of 7.8125 kHz. The
latter is derived from a balanced, low-impedance 4 MHz crystal oscillator
(pin Q1, Q2), whose output signal is divided by Q = 512.
The phase detector has two outputs UP and DOWN that drive the two current
sources I+ and I– of a charge pump. If the negative edge of the divided VCO
signal appears prior to the negative edge of the reference signal, the I+
current source pulses for the duration of the phase difference. In the reverse
case the I– current source pulses.
PD, UD
When the two signals are in phase, the charge-pump output (PD) goes high-
impedance (PLL is locked). An active low-pass filter integrates the current
pulses to generate the tuning voltage for the VCO (internal amplifier an
external transistor at the UD output and an external RC circuitry). The
charge-pump output can also be set to high-impedance state when control
bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter
over a long period in the high-impedance state as a result of self-discharge
in the peripheral circuitry. UD can be disconnected internally by the control
bit OS to enable external adjustments.
By means of a control bit 5I the pump current can be switched between two
values by software. This switchover permits alteration of the control
response of the PLL in the locked-in state. In this way different VCO gains in
the different TV bands can be compensated for example.
Semiconductor Group
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