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HYB5116405BJBT-50- Datasheet, PDF (26/28 Pages) Siemens Semiconductor Group – 4M x 4-Bit Dynamic RAM 2k & 4k Refresh | |||
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HYB5116(7)405BJ/BT-50/-60/-70
4M x 4-EDO DRAM
Test Mode
As the HYB 5116(7)405BJ/BT is organized internally as 1M x 16-bits, a test mode cycle using 4:1
compression can be used to improve test time. Note that in the 4M x 4 version the test time is
reduced by 1/4 for a N test pattern.
In a test mode âwriteâ the data from each I/O pin is written into four 1M blocks simultaneously (all
â1â s or all â0â s). In test mode âreadâ each I/O output is used for indicating the test mode result. If
the internal four bits are equal, the I/O would indicate a â1â. If they were not equal, the I/O would
indicate a â0â. The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit
from test mode, a âCAS before RAS refreshâ, âRAS only refreshâ or âHidden refreshâ can be
used.Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other
addresses are donât care.
Semiconductor Group
26
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