HYB3117800BSJ-50 Datasheet, PDF (25/26 Pages) Siemens Semiconductor Group – 2M x 8-Bit Dynamic RAM

HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Test Mode
As the HYB 3117800BSJ is organized internally as 1M x 16-bits, a test mode cycle using 2:1
compression can be used to improve test time. Note that in the 2M x 8 version the test time is
reduced by 1/2 for a N test pattern.
In a test mode “write” the data from each I/O pin is written into two 1M blocks simultaneously (all “1”
s or all “0” s). In test mode “read” each I/O output is used for indicating the test mode result. If the
internal two bits are equal, the I/O would indicate a “1”. If they were not equal, the I/O would indicate
a “0”. The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test
mode, a “CAS before RAS refresh”, “RAS only refresh” or “Hidden refresh” can be used. Refresh
during test mode operation can be performed by normal read cycles or by WCBR refresh cylces.
Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other
addresses are don’t care.
Semiconductor Group
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