PSB7115 Datasheet, PDF (248/264 Pages) Siemens Semiconductor Group – Enhanced ISDN Data Access Controller ISAR 34

PSB 7115
Detailed Register Description
Host/ISAR 34 Control Register Low
7
6
5
Write/Read Address 05h
4
3
2
1
0
The LSB of the control word contains the number of additional bytes in the mailbox,
which depends on the message specified by the HIS/IIS register.
ISAR 34 Interrupt Acknowledge Bit
Write
Address 04h
7
6
5
4
3
2
1
0
–
–
–
–
–
–
– IIA
IIA … ISAR 34 Interrupt Acknowledge
After reading a complete message from the ISAR 34 mailbox, the host sets IIA to
‘0’ to indicate to the ISAR 34, that the current message transfer is complete and
a new message transfer may be started.
ISAR 34 Interrupt Status
Read
Address 04h
7
6
5
4
3
2
1
0
IIS
The ISAR 34 interrupt status register (IIS) contains the source of the interrupt, i.e. buffer
0, 1, 2 or 3, the kind of indication (configuration, status or received data) and the
indication source (buffer, SART, pump or IOM-2).
Semiconductor Group
248
02.98