SLX24C0816P Datasheet, PDF (22/27 Pages) Siemens Semiconductor Group – 8/16 Kbit 1024/2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection Mode

SLx 24C08/16/P
7.3 Protection Bit Read
The byte sequence for random bit read is shown in figure 17.
Bus Activity
Master
S
T _Command
A _Byte
R _CSW
T
EEPROM
Address
EEA n
S
T _Command
A _Byte
R _CSW
T
Control
Byte
CTR
A
A
S
C
C
T
K
K
O
P
SDA Line S
Bus Activity
EEPROM
0
0000 S
A
A
C
C
K
K
b = Protection Bit
0
00 b
b
b
P
A
A Data
Data
... ^A
C
C Byte n Byte n+1
C
K
K
K
IED02139
Figure 17
Byte Sequence for Protection Bit Read
The first command byte CSW followed by the control byte EEA addresses the protection
bit to be read. The second command byte CSW is followed by the control byte 00_H for
protection bit read. The first bit (MSB) of the transferred byte is the protection bit of the
addressed page. The other 7 bits are not valid. The page protection status is indicated
as following
Protection Bit = 1: A normal write operation changes the data in the associated page
Protection Bit = 0: The data in the associated page are protected against changes.
If the master acknowledges a byte with a low state of the SDA line, the protection bit of
the next page can be read as the first bit of the following byte. If the master releases the
SDA line, a STOP condition has to complete the read procedure. Any number of bytes
with a page protection status at the first bit position can be requested by the master. If
the bit of the uppermost page has been addressed, the counter has its overflow to the
lowest address according to the first page.
Semiconductor Group
22
1998-07-27