SDA5275P Datasheet, PDF (19/30 Pages) Siemens Semiconductor Group – ICs for Consumer Electronics MEGATEXT and MEGATEXT PLUS ICs

SDA 5273 / 75
SDA 5273-2 / 75-2
Characteristics (cont’d)
T_A = 0 to 70 °C
Parameter
Symbol Limit Values Unit Test Condition
min. typ. max.
DRAM-Interface (see diagram 5)
The external DRAM is operated in page mode.
The timing of the DRAM-interface signals are specified below.
Cycle time
t_WC
Address hold time from RAS t_RAH
Address hold time from CAS t_CAH
Address set-up time from
t_ASR
RAS
420 500 550 ns
25
ns
60
ns
5
ns
Address set-up time from
t_ASC
5
ns
CAS
L-time RAS
t_RASP
280
ns
L-time CAS
t_CASL
70
ns
H-time RAS
t_RP
140
ns
H-time CAS
t_CP
70
ns
Refresh period
20
ms
Write Cycle
L-time WE
t_WEL
210
Data set-up time to CAS
t_DS
100
WE set-up time to CAS
t_RCS
0
Data hold time from CAS
t_DH
55
Data hold time from WE
t_OHZ
Read Cycle
H-time WE (output enable) t_OEL
210
Access time from CAS
t_CAC
Data hold time of DRAM
t_OFF
40
ns
ns
ns
ns
10 ns
ns
60 ns
ns
Semiconductor Group
19
1997-09-01