SDA5275P Datasheet, PDF (17/30 Pages) Siemens Semiconductor Group – ICs for Consumer Electronics MEGATEXT and MEGATEXT PLUS ICs

SDA 5273 / 75
SDA 5273-2 / 75-2
Characteristics (cont’d)
T_A = 0 to 70 °C
Parameter
Symbol Limit Values Unit Test Condition
min. typ. max.
M3L-Mode Timing (cont’d)
Set-up time SDA to I²CEN- t_IM
400
ns
rising edge
Set up time I²CEN to SDA- t_IS
400
ns
falling edge
I²CEN-high time
t_IH
Delay from SCL-falling edge t_DO
until SDA-open drain output
stage changes impedance
1000
400
ns
600 ns
L-SDA level output
impedance
100
Ω
The resulting delay of SDA-output data is the sum of the open drain stage plus the time
determined by the bus capacitance and the external pullup resistor or the impedance of the
internal open drain pulldown transistor respectively.
Wait condition
I²CEN = 0
To force the M3L-master to interrupt the transmission sequence until MEGATEXT is ready for
more data, MEGATEXT can force down SCL after the transmission of a complete byte. At that
time the bus master has to switch its SCL-output to high impedance and check the state of SCL
afterwards.During SCL check I²CEN has to be low.
Delay from SCL-rising edge t_DWAIT 500
to SCL forced low for WAIT-
condition
750 ns
An internal pullup transistor restores SCL high level at the end of the WAIT-condition.
SCL-pullup time at the end of t_RWAIT 70
WAIT
100 ns
Reference Voltage: V_REF
Voltage level
V_REF
2.8 3.0 3.5 V
Input leakage current
I_l
– 10
10
µA V_REF = 3 V
V_REF influences the DAC-range, the CVBS-output at pin TCSQ and the CVBS-ADC range.
Semiconductor Group
17
1997-09-01