SAB82525H-V21 Datasheet, PDF (13/126 Pages) Siemens Semiconductor Group – High-Level Serial Communication Controller Extended

SAB 82525
SAB 82526
SAF 82525
SAF 82526
Pin Definitions and Functions (cont’d)
Pin No.
Symbol
P-LCC P-MQFP
28 33 INT
Input (I) Function
Output (O)
oD
Interrupt Request
The signal is activated, when the HSCX requests an
interrupt.
The CPU may determine the particular source and cause of
the interrupt by reading the HSCX’s interrupt status
registers. (ISTA, EXIR).
INT is an open drain output, thus the interrupt requests
outputs of several HSCX’s can be connected to one
interrupt input in a "wired-or" combination.
This pin must be connected to a pull-up resistor.
30 35
29 34
DACKA I
DACKB
DMA Acknowledge (channel A/channel B)
When low, this input signal from the DMA controller notifies,
the HSCX, that the requested DMA cycle controlled via
DRQxx (pins 37–40) is in progress, i.e. the DMA controller
has achieved bus mastership from the CPU and will start
data transfer cycles (either read or write).
Together with RD, if DMA has been requested from the
receiver, or with WR, if DMA has been requested from the
transmitter, this input works like CS to enable a data byte to
be read from or written to the top of the receive or transmit
FIFO of the specified channel.
If DACKn is active, the input on pins A0–A6 is ignored and
the FIFOs are implicitly selected.
If the DACKn signals are not used, these pins must be
connected to V_DD.
34 39
31 36
AxCLK I
A
AxCLK
B
Alternative Clock (channel A/channel B)
These pins realize several input functions. Depending on
the selected clock mode, they may supply either a
– CD (= Carrier Detect) modem control or general purpose
input.
This pin can be programmed to functions as receiver
enable if the "auto start" feature is selected (CAS bit in
XBCH set). The state at this pin can be read from VSTR
register,
– or a receive strobe signal (clock mode 1)
– or a frame synchronization signal in time-slot oriented
operation mode (clock mode 5)
– or, together with RxCLK, a crystal connection for the
internal oscillator (clock mode 4, 6, 7, AxCLK A only).
Semiconductor Group
13