HYM64V8005GU-50 Datasheet, PDF (11/17 Pages) Siemens Semiconductor Group – 3.3V 8M x 64-Bit EDO-DRAM Module 3.3V 8M x 72-Bit EDO-DRAM Module

HYM 64(72)V8005/45GU-50/-60
8M x 64/72 DRAM Module
AC Characteristics ⁵⁾⁶⁾
T_A = 0 to 70 °C,V_CC = 3.3 V ± 0.3 V, t_T = 2 ns
Parameter
Symbol
Limit Values
-50
-60
min. max. min. max.
common parameters
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period for 4k-refresh
Refresh period for 8k-refresh
t_RC
84
–
104
–
t_RP
30
–
40
–
t_RAS
50 10k 60 10k
t_CAS
8
10k 10 10k
t_ASR
0
–
0
–
t_RAH
8
–
10
–
t_ASC
0
–
0
–
t_CAH
8
–
10
–
t_RCD
12
37
14
45
t_RAD
10
25
12
30
t_RSH
13
15
–
t_CSH
40
50
–
t_CRP
5
–
5
–
t_T
1
50
1
50
t_REF
–
64
–
64
t_REF
–
128
–
128
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
16E
Note
7
Read Cycle
Access time from RAS
t_RAC
Access time from CAS
t_CAC
Access time from column address
t_AA
OE access time
t_OEA
Column address to RAS lead time
t_RAL
Read command setup time
t_RCS
Read command hold time
t_RCH
Read command hold time referenced to t_RRH
RAS
CAS to output in low-Z
t_CLZ
Output buffer turn-off delay
t_OFF
–
50
–
60
ns 8, 9
–
13
–
15
ns 8, 9
–
25
–
30
ns 8,10
–
13
–
15
ns
25
–
30
–
ns
0
–
0
–
ns
0
–
0
–
ns 11
0
–
0
–
ns 11
0
–
0
–
ns 8
0
13
0
15
ns 12
Semiconductor Group
11