PEB2035 Datasheet, PDF (100/134 Pages) Siemens Semiconductor Group – ICs for Communications (Advanced CMOS Frame Aligner)

PEB 2035
BSEL ... Bank Select
0 ... If bit CPY.SW is set, control register addresses 06 to 09 select the clear channel registers
CCB1, CCB2, CCB3 and register ACR.
1 ... If bit CPY.SW is set, control register addresses 01, 06 to 09 select registers EMOD and the
idle channel registers ICB1, ICB2, ICB3. Address 09 is reserved for future extensions.
DCPY ... Disable Channel Parity Check
0 ... Normal operation.
1 ... Disables the channel parity check selected by this register. This bit should be set at least
one time-slot before changing the channel address.
CPA4 ... CPA0 ... Channel Address For Parity Check
CPA = 0 ... 24 selects the channel.
Channel Loop Back (WRITE)
LOOP
7
AIA
SLB DLOP CLA4
0
CLA0
(03)
AIA ... Alarm Interrupt Acknowledge
(NOT READABLE)
A ‘1’ written to this bit location clears the alarm interrupt signal at port AINT if the alarm
interrupt mode is enabled via bit CCR.AINT and register MASK or XC1.MCA.
Resetting this bit is not necessary.
SLB ... Enable Signaling Loop Back
If channel loop back is enabled by programming register LOOP
0 ... loop back of signaling data is suppressed, e.g. a ‘clear’ channel without bitrobbing data is
looped back.
1 ... channel data and signaling data will be looped back.
DLOP ... Disable Channel Loop Back
0 ... Normal operation.
1 ... Disables the channel loop back selected by this register. This bit should be set at least one
time-slot before changing the channel address.
CLA4 ... CLA0 ... Channel Address For Loop Back
CLA = 1 ... 24 selects the channel.
CLA =
0 disables channel loop back.
During loop back, the contents of the associated outgoing channel at ports XDOP, XDOM is
equal to the idle channel code programmed in register IDLE.
Semiconductor Group
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