SDA2526-5 Datasheet, PDF (1/12 Pages) Siemens Semiconductor Group – Nonvolatile Memory 2-Kbit E2PROM with I2C Bus

Nonvolatile Memory 2-Kbit E²PROM
with I²C Bus
SDA 2526-5
Preliminary Data
MOS IC
Features
q Word-organized programmable nonvolatile memory in
n-channel floating-gate technology (E²PROM)
q 256 × 8-bit organization
q Supply voltage 5 V
q Serial 2-line bus for data input and output (I²C Bus)
q Reprogramming mode, 10 ms erase/write cycle
q Reprogramming by means of on-chip control (without
external control)
q Check for end of programming process
q Data retention > 10 years
q More than 10⁴ reprogramming cycles per address
q Compatible with SDA 2526. Exceptions: Conditions for
total erase and current consumption I_CC
Type
SDA 2526-5
Ordering Code
Q67100-H5095
P-DIP-8-1
Package
P-DIP-8-1
Circuit Description
I²C Bus Interface
The I²C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.
It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external
pull-up resistor to V_CC (open drain output stage).
The possible operational states of the I²C Bus are shown in figure 1. In the quiescent state, both
lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains
"1", information changes on the data bus indicate the start or the end of data transfer between two
components.
The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" is a stop
condition. During a data transfer the information on the data bus will only change while the clock line
SCL is "0". The information on SDA is valid as long as SCL is "1".
In conjunction with an I²C Bus system, the memory component can operate as a receiver and as a
transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is
always transmitted in byte-organized form. Between the falling edge of the eighth clock pulse and
a ninth acknowledge clock pulse, the memory component sets the SDA-line to low as a confirmation
of reception, if the chip select conditions have been met. During the output of data, the data output
of the memory is high in impedance during the ninth clock pulse (acknowledge master).
The signal timing required for the operation of the I²C Bus is summarized in figure 2.
Semiconductor Group
17
07.94