LH28F320S3TD-L10 Datasheet, PDF (32/51 Pages) Sharp Electrionic Components – 32 M-bit (2 MB x 8/1 MB x 16 x 2-Bank) Smart 3 Dual Work Flash Memory

LH28F320S3TD-L10
Start
Write 60H,
Block Address
Write 01H,
Block Address
Read
Status Register
0
SR.7 =
1
Full Status
Check if Desired
Set Block Lock-Bit
Complete
BUS
OPERATION ^COMMAND
COMMENTS
Write
Set Block Data = 60H
Lock-Bit Setup Addr = Block Address
Write
Set Block Data = 01H
Lock-Bit Confirm Addr = Block Address
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block set operations.
Full status check can be done after each block lock-bit set
operation or after a sequence of block lock-bit set operations.
Write FFH after the last block lock-bit set operation to place
device in read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 = ¹
0
VPP Range Error
1
SR.1 =
0
1
SR.4, 5 =
0
Device Protect Error
Command Sequence
Error
1
SR.4 =
0
Set Block Lock-Bit
Successful
Set Block Lock-Bit
Error
BUS
OPERATION ^COMMAND
COMMENTS
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
WP# = VIL
Standby
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Check SR.4
1 = Set Block Lock-Bit Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple block
lock-bits are set before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
Fig. 10 Set Block Lock-Bit Flowchart
- 32 -