LH540215 Datasheet, PDF (19/48 Pages) Sharp Electrionic Components – 512 x 18 / 1024 x 18 Synchronous FIFO

512 x 18/1024 x 18 Synchronous FIFO
LH540215/25
DESCRIPTION OF SIGNALS AND
OPERATING SEQUENCES (cont’d)
locked paralleled, cascaded ‘master’ or ‘first-load,’ and
cascaded ‘slave.’ The designations ‘master’ and ‘slave’
pertain to IDT-compatible depth cascading. Tables 1 and
2 show the signal encodings which select each grouping
mode.
In standalone operation, WXI/WEN2 and RXI/REN2
both must be grounded so that the FIFO comes up in the
standalone grouping mode after a reset operation. In
interlocked-paralleled operation, WXI/WEN2 is tied to
FF of the other paralleled FIFO, and RXI/REN2 is tied
to EF of that same other FIFO. This interconnection
scheme ensures that both FIFOs will operate
together, and remain coordinated, regardless of tim-
ing skews.
In cascaded operation, WXI/WEN2 is connected to the
WXO (Write Expansion Output; actually WXO/HF) output
of the previous FIFO in the cascade. RXI/REN2 is likewise
connected to the RXO (Read Expansion Output; actually
RXO/EF2) output of that previous FIFO. A reset operation
forces WXO/HF and RXO/EF2 HIGH for each FIFO;
consequently, all FIFOs with their WXI/WEN2 and
RXI/REN2 inputs thus connected come up in one of the
two cascaded grouping modes, according to whether
their FL/RT inputs are grounded or tied HIGH. (See again
Tables 1 and 2.)
READ EXPANSION INPUT/READ ENABLE 2
(RXI/REN2)
RXI/REN2 is a dual-purpose signal. It is one of four
input signals which select the grouping mode in which the
FIFO operates after being reset; the other three of these
input signals are FL/RT, WXI/WEN2, and EMODE. There
are four possible grouping modes: standalone, inter-
locked-paralleled, cascaded ‘master’ or ‘first-load,’ and
cascaded ‘slave.’ The designations ‘master’ and ‘slave’
pertain to IDT-compatible depth cascading. Tables 1 and
2 show the signal encodings which select each grouping
mode.
In standalone operation, WXI/WEN2 and RXI/REN2
both must be grounded, so that the FIFO comes up in the
standalone grouping mode after a reset operation. In
interlocked-paralleled operation, WXI/WEN2 is tied to
FF of the other paralleled FIFO, and RXI/REN2 is tied
to EF of that same other FIFO. This interconnection
scheme ensures that both FIFOs will operate to-
gether, and remain coordinated, regardless of timing
skews.
In cascaded operation, RXI/REN2 is connected to
RXO (Read Expansion Output; actually RXO/EF2)) of the
previous FIFO in the cascade. WXI/WEN2 is likewise
connected to WXO (Write Expansion Output; actually
WXO/HF) output of that previous FIFO. A reset operation
BOLD ITALIC = Enhanced Operating Mode
forces RXO/EF2 and WXO/HF HIGH for each FIFO;
consequently, all FIFOs with their RXI/REN2 and
WXI/WEN2 inputs thus connected come up in one of the
two IDT-compatible cascaded grouping modes, accord-
ing to whether their FL/RT inputs are grounded or tied
HIGH. (See again Tables 1 and 2.)
Data Outputs
DATA OUT (Q0 – Q17)
Data, programmable-flag-offset values, and Control-
Register codes are output from the FIFO as 18-bit words
on Q0 – Q17. Unused bit positions in offset-value words
and Control-Register words are zero-filled.
Control/Status Outputs
FULL FLAG (FF)
FF goes LOW whenever the FIFO is completely full.
That is, whenever the FIFO’s internal write pointer has
completely caught up with its internal read pointer;so that,
if another word were to be written, it would have to
overwrite the unread word which is now in position for
reading out by the next requested read operation. Under
these conditions, the FIFO is filled to its nominal capacity,
which is 512 18-bit words for the LH540215 or 1024 18-bit
words for the LH540225 respectively. Write operations
are inhibited whenever FF is LOW, regardless of the
assertion or deassertion of Write Enable (WEN).
If the FIFO has been reset by asserting RS (LOW), FF
initially is HIGH. But, whenever no read operations have
been performed since the completion of the reset opera-
tion, FF goes LOW after 512 write operations for the
LH540215, or after 1024 write operations for the
LH540225. (See Table 4.)
FF gets updated after a LOW-to-HIGH transition of the
Write Clock (WCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
PAF goes LOW whenever the FIFO is ‘almost’ full;
that is, whenever subtracting the value of the FIFO’s
internal read pointer from the value of its internal write
pointer yields a difference which is less than the value of
the Programmable-Almost-Full-Flag Offset ‘p.’ The sub-
traction is performed using modular arithmetic, modulo
the total nominal number of 18-bit words in the FIFO’s
physical memory, which is 512 for the LH540215 or 1024
for the LH540225 respectively.
The default value of ‘p’ after the completion of a reset
operation is one-eighth of the total number of words in the
FIFO-memory array, minus one: 6310 for the LH540215
or 12710 for the LH540225 respectively. However, ‘p’ may
be set to any value which does not exceed this total
nominal number of words for the device, as explained in
the description of Load (LD).
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