LH540215 Datasheet, PDF (1/48 Pages) Sharp Electrionic Components – 512 x 18 / 1024 x 18 Synchronous FIFO

LH540215/25
FEATURES
• Fast Cycle Times: 20/25/35 ns
• Pin-Compatible Drop-In Replacements for
IDT72215B/25B FIFOs
• Choice of IDT-Compatible or Enhanced Operating
Mode; Selected by an Input Control Signal
• Device Comes Up into One of Two Known Default
States at Reset Depending on the State of the
EMODE Control Input: Programming is Allowed, but
is not Required
• Internal Memory Array Architecture Based on CMOS
Dual-Port SRAM Technology, 512 × 18 or 1024 × 18
• ‘Synchronous’ Enable-Plus-Clock Control at Both
Input Port and Output Port
• Independently-Synchronized Operation of Input Port
and Output Port
• Control Inputs Sampled on Rising Clock Edge
• Most Control Signals Assertive-LOW for
Noise Immunity
512 × 18 / 1024 × 18 Synchronous FIFO
• May be Cascaded for Increased Depth, or
Paralleled for Increased Width
• Five Status Flags: Full, Almost-Full, Half-Full,
Almost-Empty, and Empty; ‘Almost’ Flags are
Programmable
• In Enhanced Operating Mode, Almost-Full,
Half-Full, and Almost-Empty Flags can be Made
Completely Synchronous
• In Enhanced Operating Mode, Duplicate Enables
for Interlocked Paralleled FIFO Operation, for
36-Bit Data Width, when Selected and
Appropriately Connected
• In Enhanced Operating Mode, Disabling
Three-State Outputs May be Made to Suppress
Reading
• Data Retransmit Function
• TTL/CMOS-Compatible I/O
• Space-Saving 68-Pin PLCC Package, and 64-Pin
TQFP Package
RS
RESET
LOGIC
FL/RT
WXI/WEN₂
WXO/HF
RXI/REN₂
RXO/EF₂
EXPANSION
LOGIC
WCK
WEN
WXI/WEN₂
INPUT
PORT
CONTROL
LOGIC
FIFO
MEMORY ARRAY
512 x 18/1024 x 18
WRITE
POINTER
READ
POINTER
OUTPUT
PORT
CONTROL
LOGIC
FF
PAF
WXO/HF
D₀ - D₁₇
LD
INPUT
PORT
EMODE
BOLD ITALIC = Enhanced Operating Mode.
DEDICATED AND
PROGRAMMABLE
STATUS FLAGS
PROGRAMMABLE
REGISTERS
OUTPUT
PORT
Figure 1. LH540215/25 Block Diagram
RCK
REN
RXI/REN₂
EF
PAE
RXO/EF₂
OE
Q₀ - Q₁₇
540215-1
BOLD ITALIC = Enhanced Operating Mode
1