LH28F004SU-Z1 Datasheet, PDF (14/32 Pages) Sharp Electrionic Components – 4M (512K × 8) Flash Memory

LH28F004SU-Z1
4M (512K × 8) Flash Memory
START
READ COMPATIBLE
STATUS REGISTER
CSR.7 = ⁰
1
WRITE FBH
WRITE DATA/A₁₀
WRITE
DATA/ADDRESS
READ COMPATIBLE
STATUS REGISTER
0
CSR.7 =
1
1 ^(NOTE)
CSR.4, 5 =
0
(Apply to LH28F004SU, x8, 40TSOP)
BUS
OPERATION
COMMAND
COMMENTS
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Write
2-Byte
Write
D = FBH
A=X
Write
D = WD
A₁₀ = 0 loads low byte
of Data Register.
A₁₀ = 1 loads high byte
of Data Register.
Other Addresses = X
Write
D = WD
A = WA
Internally, A₁₀ is automatically
complemented to load the
alternate byte location of the
Data Register.
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
CSR Full Status Check can be done after each 2-Byte Write,
or after a sequence of 2-Byte Writes.
Write FFH after the last operation to reset device to read
array mode.
See Command Bus Cycle notes for description of codes.
ANOTHER _YES
2-BYTE
WRITE
NO
OPERATION COMPLETE
28F004SUT-Z1-9
Figure 9. Two-Byte Serial Writes with Compatible Status Registers (40-pin TSOP)
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