LH28F008SC-V Datasheet, PDF (12/40 Pages) Sharp Electrionic Components – 8 M-bit (1 MB x 8) Smart 5

4.1 Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, byte write or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or Byte
Write Suspend command. The Read Array
command functions independently of the VPP
voltage and RP# can be VIH or VHH.
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and master lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the VPP voltage and RP# can be
VIH or VHH. Following the Read Identifier Codes
command, the following information can be read :
Table 4 Identifier Codes
CODE
Manufacture Code
Device Code
Block Lock Configuration
• Block is Unlocked
• Block is Locked
• Reserved for Future Use
Master Lock Configuration
• Device is Unlocked
• Device is Locked
• Reserved for Future Use
ADDRESS DATA
00000H
89
00001H
A6
X0002H ^{(NOTE 1)}
DQ0 = 0
DQ0 = 1
DQ1-7
00003H
DQ0 = 0
DQ0 = 1
DQ1-7
NOTE :
1. X selects the specific block lock configuration code to be
read. See Fig. 2 for the device identifier code memory
map.
LH28F008SC-V/SCH-V
4.3 Read Status Register Command
The status register may be read to determine when
a block erase, byte write, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs. OE# or CE# must toggle to
VIH before further reads to update the status
register latch. The Read Status Register command
functions independently of the VPP voltage. RP#
can be VIH or VHH.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied VPP voltage. RP# can
be VIH or VHH. This command is not functional
during block erase or byte write suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
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