LRS1805A Datasheet, PDF (11/57 Pages) Sharp Electrionic Components – Stacked Chip 64M (x16) Flash Memory + 16M (x16) Smartcombo RAM

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LRS1805A
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8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the
suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.
9. Full chip erase operation can not be suspended.
10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when F-WP is V_IL.
When F-WP is V_IH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.
11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.