LH28F800SU Datasheet, PDF (10/38 Pages) Sharp Electrionic Components – 8M (512K × 16, 1M × 8) Flash Memory

LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
LH28F008SA-Compatible Mode Command Bus Definitions
COMMAND
Read Array
Intelligent Identifier
Read Compatible Status Register
Clear Status Register
Word/Byte Write
Alternate Word/Byte Write
Block Erase/Confirm
Erase Suspend/Resume
FIRST BUS CYCLE
OPER. ADDRESS DATA
Write
X
FFH
Write
X
90H
Write
X
70H
Write
X
50H
Write
X
40H
Write
X
10H
Write
X
20H
Write
X
B0H
SECOND BUS CYCLE
OPER. ADDRESS DATA
Read
AA
AD
Read
IA
ID
Read
X
CSRD
Write
WA
WD
Write
WA
WD
Write
BA
D0H
Write
X
D0H
NOTE
1
2
3
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don’t Care
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions.
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