SGM8061 Datasheet, PDF (9/14 Pages) SG Micro Corp – 500MHz, Rail-to-Rail Output CMOS Operational Amplifier

APPLICATION NOTES
Driving Capacitive Loads
The SGM806x family is optimized for bandwidth and speed,
not for driving capacitive loads. Output capacitance will create
a pole in the amplifier’s feedback path, leading to excessive
peaking and potential oscillation. If dealing with load
capacitance is a requirement of the application, the two
strategies to consider are (1) using a small resistor in series
with the amplifier’s output and the load capacitance and (2)
reducing the bandwidth of the amplifier’s feedback loop by
increasing the overall noise gain.
Figure 1 shows a unity gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
SGM8061
V_IN
R_ISO
V_OUT
C_LOAD
Figure 1. Series Resistor Isolating Capacitive Load
Power-Supply Bypassing and Layout
The SGM806x family operates from either a single +2.7V to
+5.5V supply or dual ±1.35V to ±2.75V supplies. For
single-supply operation, bypass the power supply V_DD with a
0.1µF ceramic capacitor which should be placed close to the
VDD pin. For dual-supply operation, both the VDD and the VSS
supplies should be bypassed to ground with separate 0.1µF
ceramic capacitors. 2.2µF tantalum capacitor can be added for
better performance.
Good PC board layout techniques optimize performance by
decreasing the amount of stray capacitance at the op amp’s
inputs and output. To decrease stray capacitance, minimize
trace lengths and widths by placing external components as
close to the device as possible. Use surface-mount
components whenever possible.
For the high speed operational amplifier, soldering the part to
the board directly is strongly recommended. Try to keep the
high frequency big current loop area small to minimize the EMI
(electromagnetic interfacing).
V_DD
10µF
0.1µF
V_DD
10µF
0.1µF
Vn
SGM8061
Vp
Vn
V_{OUT Vp}
SGM8061
V_OUT
10µF
V_SS(GND)
0.1µF
V_SS
Figure 2. Amplifier with Bypass Capacitors
Grounding
A ground plane layer is important for high speed circuit design.
The length of the current path speed currents in an inductive
ground return will create an unwanted voltage noise. Broad
ground plane areas will reduce the parasitic inductance.
Input-to-Output Coupling
To minimize capacitive coupling, the input and output signal
traces should not be parallel. This helps reduce unwanted
positive feedback.
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