SGM708 Datasheet, PDF (9/12 Pages) SG Micro Corp – Low-Cost, Microprocessor Supervisory Circuit

SGM708
APPLICATION NOTES
Ensuring a Valid RESET Output Down to
V_CC = 0V
When V_CC falls below 1V, the SGM708 RESET output no
longer sinks current—it becomes an open circuit.
High-impedance CMOS logic inputs can drift to undetermined
voltages if left undriven. If a pull-down resistor is added to the
RESET pin as shown in Figure 1, any stray charge or leakage
currents will be drained to ground, holding RESET low.
Resistor value (R1) is not critical. It should be about 100kΩ,
large enough not to load RESET and small enough to pull
RESET to ground.
SGM708
RESET
R1
Figure 1. RESET Valid to Ground Circuit
Monitoring Voltages Other Than the
Unregulated DC Input
Monitor voltages other than the unregulated DC by connecting
a voltage divider to PFI and adjusting the ratio appropriately. If
required, add hysteresis by connecting a resistor (with a value
approximately 10 times the sum of the two resistors in the
potential divider network) between PFI and PFO . A capacitor
between PFI and GND will reduce the power-fail circuit’s
sensitivity to high-frequency noise on the line being monitored.
RESET can be asserted on other voltages in addition to the
+5V VCC line. Connect PFO to MR to initiate a RESET
pulse when PFI drops below 1.25V. Figure 2 shows the
SGM708 configured to assert RESET when the +5V supply
falls below the reset threshold, or when the +12V supply falls
below approximately 11V.
+12V +5V
1MΩ
1%
130kΩ
1%
V_CC
RESET
SGM708 _MR
PFI _{GND PFO}
TO µP
Figure 2. Monitoring Both +5V and +12V
Low-Cost, Microprocessor
Supervisory Circuit
Monitoring a Negative Voltage
The power-fail comparator can also monitor a negative supply
rail (Figure 3). When the negative rail is good (a negative
voltage of large magnitude), PFO is low, and when the
negative rail is degraded (a negative voltage of lesser
magnitude), PFO is high. By adding the resistors and
transistor as shown, a high PFO triggers reset. As long as
PFO remains high, the SGM708 will keep reset asserted
( RESET = low, RESET = high). Note that this circuit’s accuracy
depends on the PFI threshold tolerance, the VCC line, and the
resistors.
+5V
VCC
R1
MR
SGM708
100kΩ
PFI
100kΩ
PFO
2N3904
R2
V-
+5V
MR _0V
+5V
PFO _0V
RESET
GND
TO μP
V-
VTRIP
0V
5 – 1.25
R1
=
1.25 - VTRIP
R2
VTRIP < 0
Figure 3. Monitoring a Negative Voltage
Interfacing to μPs with Bidirectional Reset
Pins
μPs with bidirectional reset pins, such as the Motorola 68HC11
series, can contend with the SGM708 RESET output. If, for
example, the RESET output is driven high and the
Microprocessor wants to pull it low, indeterminate logic levels
may result. To correct this, connect a 4.7kΩ resistor between
the RESET output and the μP reset I/O, as in Figure 4. Buffer
the RESET output to other system components.
BUFFRED RESET TO OTHER SYSTEM COMPONENTS
VCC
SGM708
RESET
GND
4.7kΩ
VCC
Microprocessor
RESET
GND
Figure 4. Interfacing to Microprocessors with Bidirectional
Reset I/O
SG Micro Corp
9
www.sg-micro.com