SGM804 Datasheet, PDF (8/11 Pages) SG Micro Corp – Capacitor-Adjustable Reset Timeout Delay

SGM804
Low-Power, SOT µP Reset Circuit with
Capacitor-Adjustable Reset Timeout Delay
APPLICATIONS INFORMATION
Negative-Going V_CC Transients
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, this supervisor is
relatively immune to short-duration negative-going
transients (glitches). The graph Maximum Transient
Duration vs. Reset Threshold Overdrive in the Typical
Performance Characteristics shows this relationship.
The area below the curve of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negative-going
pulse applied to V_CC, starting above the actual reset
threshold (V_TH) and ending below it by the magnitude
indicated (reset-threshold overdrive). As the magnitude
of the transient decreases (further below the reset
threshold), the maximum allowable pulse width-
decreases. Typically, a V_CC transient that goes 100mV
below the reset threshold and lasts 50µs or less does not
cause a reset pulse to be issued.
Ensuring a Valid RESET Down to V_CC = 0
When V_CC falls below 1V, RESET current-sinking
(sourcing) capabilities decline drastically. In the case of
the SGM804, high-impedance CMOS-logic inputs
connected to _RESET can drift to undetermined voltages.
This presents no problems in most applications, since
most µPs and other circuitry do not operate with V_CC
below 1V.
VCC
VCC
SGM804
RESET
GND
100kΩ
Figure 2. Ensuring RESET Valid to V_CC = 0
Layout Consideration
SRT is a precise current source. When developing the
layout for the application, be careful to minimize board
capacitance and leakage currents around this pin. Traces
connected to SRT should be kept as short as possible.
Traces carrying high-speed digital signals and traces with
large voltage potentials should be routed as far from SRT
as possible. Leakage current and stray capacitance (e.g.,
a scope probe) at this pin could cause errors in the reset
timeout period. When evaluating these parts, use clean
prototype boards to ensure accurate reset periods.
In those applications where RESET must be valid down
to zero, adding a pull down resistor between _RESET and
ground sinks any stray leakage currents, holding RESET
low (Figure 2). The value of the pull down resistor is not
critical; 100kΩ is large enough not to load _RESET and
small enough to pull RESET to ground.
SG Micro Corp
8
www.sg-micro.com