SGM804 Datasheet, PDF (7/11 Pages) SG Micro Corp – Capacitor-Adjustable Reset Timeout Delay

SGM804
Low-Power, SOT µP Reset Circuit with
Capacitor-Adjustable Reset Timeout Delay
DETAILED DESCRIPTION
Reset Output
The reset output is typically connected to the reset input
of a µP. A µP’s reset input starts or restarts the µP in a
known state. The SGM804 µP supervisory circuit
provides the reset logic to prevent code-execution errors
during power-up, power-down, and brownout conditions.
RESET changes from high to low whenever VCC drops
below the threshold voltage. Once V_CC exceeds the
threshold voltage, RESET remains low for the capacitor-
adjustable reset timeout period.
This device output is guaranteed valid for V_CC > 1V.
Operating as a Voltage Detector
The SGM804 can be operated in a voltage detector mode
by floating the SRT pin. The reset delay times for V_CC
rising above or falling below the threshold are not
significantly different. The reset output is deasserted
smoothly without false pulses.
Selecting a Reset Capacitor
The reset timeout period is adjustable to accommodate a
variety of µP applications. Adjust the reset timeout period
(t_RP) by connecting a capacitor (C_SRT) between SRT and
ground. Calculate the reset timeout capacitor as follows:
C_SRT = (t_RP - 340 × 10^-6) / (2.6 × 10⁶)
where t_RP is in seconds and C_SRT is in farads.
The reset delay time is set by a current/capacitor-
controlled ramp compared to an internal 0.6V reference.
An internal 210nA ramp current source charges the
external capacitor. The charge to the capacitor is cleared
when a reset condition is detected. Once the reset
condition is removed, the voltage on the capacitor ramps
according to the formula: dV/dt = I/C. The C_SRT capacitor
must ramp to 0.6V to deassert the reset. C_SRT must be a
low-leakage (<10nA) type capacitor; ceramic is
recommended.
V_CC
V_CC
+
-
μP
V_REF
C_SRT
SRT RESET
TIMEOUT
RESET
SGM804
GND
RESET
Figure 1. Typical Operating Circuit
SG Micro Corp
7
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