SGM800 Datasheet, PDF (8/11 Pages) SG Micro Corp – Capacitor-Adjustable Reset Timeout Delay

SGM800
Low-Power, SOT µP Reset Circuit with
Capacitor-Adjustable Reset Timeout Delay
APPLICATION INFORMATION
Interfacing to Other Voltages for Logic
Compatibility
The open-drain output of the SGM800 can be used to
interface to µPs with other logic levels. As shown in
Figure 1, the open-drain output can be connected to
voltages from 0 to 5.5V. This allows for easy logic
compatibility to various µPs.
Wired-OR Reset
To allow auxiliary circuitry to hold the system in reset, an
external open-drain logic signal can be connected to the
open-drain RESET of the SGM800, as shown in Figure
2. This configuration can reset the µP, but does not
provide the reset timeout when the external logic signal is
released.
CSRT
3.3V
VCC
5.0V
-
+
SRT RESET
TIMEOUT
VREF
10kΩ
RESET
5V
SYSTEM
SGM800
GND
V_CC
V_CC
SGM800
RESET
N
GND
10kΩ
μP
RESET
Figure 1. Open-Drain RESET Output Allows Use with Multiple
Supplies
OPEN-DRAIN
LOGIC
N
Negative-Going V_CC Transients
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, this supervisor is
relatively immune to short-duration negative-going
transients (glitches). The graph Maximum Transient
Duration vs. Reset Threshold Overdrive in the Typical
Performance Characteristics shows this relationship.
The area below the curve of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negative-going
pulse applied to V_CC, starting above the actual reset
threshold (V_TH) and ending below it by the magnitude
indicated (reset-threshold overdrive). As the magnitude
of the transient decreases (further below the reset
threshold), the maximum allowable pulse width-
decreases. Typically, a V_CC transient that goes 100mV
below the reset threshold and lasts 50µs or less does not
cause a reset pulse to be issued.
Figure 2. Wired-OR Reset Circuit
Layout Consideration
SRT is a precise current source. When developing the
layout for the application, be careful to minimize board
capacitance and leakage currents around this pin. Traces
connected to SRT should be kept as short as possible.
Traces carrying high-speed digital signals and traces with
large voltage potentials should be routed as far from SRT
as possible. Leakage current and stray capacitance (e.g.,
a scope probe) at this pin could cause errors in the reset
timeout period. When evaluating these parts, use clean
prototype boards to ensure accurate reset periods.
SG Micro Corp
8
www.sg-micro.com