SGM706 Datasheet, PDF (4/12 Pages) SG Micro Corp – Low-Cost, Microprocessor Supervisory Circuit

SGM706
PIN CONFIGURATION (TOP VIEW)
Low-Cost, Microprocessor
Supervisory Circuit
MR ¹
V_CC 2
GND 3
PFI 4
SGM706
8 WDO
7 RESET
6 WDI
5 PFO
SOIC-8
PIN DESCRIPTION
PIN NAME
FUNCTION
Manual-Reset Input triggers a reset pulse when pulled below 0.8V. This active-low input has an
1
MR internal 250μA (VCC = +5V) pull-up current. It can be driven from a TTL or CMOS logic line as well as
shorted to ground with a switch.
2 V_CC Power Supply Voltage that is monitored.
3 GND 0V Ground Reference for all signals.
4
PFI
Power-Fail Voltage Monitor Input. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND
or V_CC when not used.
5
PFO
Power-Fail Output goes low and sinks current when PFI is less than 1.25V; otherwise PFO stays
high.
Watchdog Input. If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and WDO
6
WDI
goes low (BLOCK DIAGRAM). Floating WDI or connecting WDI to a high-impedance three-state
buffer disables the watchdog feature. The internal watchdog timer clears whenever reset is asserted,
WDI is three-stated, or WDI sees a rising or falling edge.
Active-Low Reset Output pulses low for 200ms when triggered, and stays low whenever V_CC is below
the reset threshold (4.65V for SGM706-L, 4.4V for SGM706-M, 4.0V for SGM706-J, 3.08V for
7 RESET ^{SGM706-T and 2.93V for SGM706-S, 2.63V for SGM706-R). It remains low for 200ms after V}CC ^rises
above the reset threshold or MR goes from low to high. A watchdog timeout will not trigger RESET
unless WDO is connected to MR.
Watchdog Output pulls low when the internal watchdog timer finishes its 1.6sec count and does not
go high again until the watchdog is cleared. WDO also goes low during low-line conditions.
8 WDO Whenever VCC is below the reset threshold, WDO stays low; however, unlike RESET , WDO does
not have a minimum pulse width. As soon as V_CC rises above the reset threshold, WDO goes high
with no delay.
SG Micro Corp
4
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