XE8801A Datasheet, PDF (95/135 Pages) Semtech Corporation – Data Acquisition with ZoomingADC™

XE8801A – SX8801R
PGA3_GAIN[6:0]
0000000
0000001
...
0000110
...
0001100
0010000
...
0100000
...
1000000
...
1111111
PGA3 Gain
GD3 (V/V)
0
1/12(=0.083)
...
6/12
...
12/12
16/12
32/12
64/12
127/12(=10.58)
Table 16-17 PGA3 gain settings
PGA3_OFFSET[6:0]
0000000
0000001
0000010
...
0010000
...
0100000
...
0111111
1000000
1000001
1000010
...
1010000
...
1100000
...
1111111
PGA3 Offset
GDoff3 (V/V)
0
+1/12(=+0.083)
+2/12
...
+16/12
...
+32/12
...
+63/12(=+5.25)
0
-1/12(=-0.083)
-2/12
...
-16/12
...
-32/12
...
-63/12(=-5.25)
Table 16-18 PGA3 offset settings
16.6.1 PGA & ADC Enabling
Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to
the word ENABLE and the coding given in Table 16-13. To reduce power dissipation, the ADC can also be inactivated
while idle.
16.6.2 PGA1
The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 16-14). The voltage V_D1 at
the output of PGA1 is:
V_D1 = GD₁ ⋅V_IN
(V)
(Eq. 5)
where GD₁ is the gain of PGA1 (in V/V) controlled with the bit PGA1_GAIN.
© Semtech 2005
16-10
www.semtech.com