XE8801A Datasheet, PDF (22/135 Pages) Semtech Corporation – Data Acquisition with ZoomingADC™

XE8801A – SX8801R
Dec reg1, reg2
Dec reg
Dec reg, eaddr
Decc reg1, reg2
Decc reg
Decc reg, eaddr
And reg,#data[7:0]
And reg1, reg2, reg3
And reg1, reg2
And reg, eaddr
Or reg,#data[7:0]
Or reg1, reg2, reg3
Or reg1, reg2
Or reg, eaddr
Xor reg,#data[7:0]
Xor reg1, reg2, reg3
Xor reg1, reg2
Xor reg, eaddr
Add reg,#data[7:0]
Add reg1, reg2, reg3
Add reg1, reg2
Add reg, eaddr
Addc reg,#data[7:0]
Addc reg1, reg2, reg3
Addc reg1, reg2
Addc reg, eaddr
Subd reg,#data[7:0]
Subd reg1, reg2, reg3
Subd reg1, reg2
Subd reg, eaddr
Subdc reg,#data[7:0]
Subdc reg1, reg2, reg3
Subdc reg1, reg2
Subdc reg, eaddr
Subs reg,#data[7:0]
Subs reg1, reg2, reg3
Subs reg1, reg2
Subs reg, eaddr
Subsc reg,#data[7:0]
Subsc reg1, reg2, reg3
Subsc reg1, reg2
Subsc reg, eaddr
Mul reg,#data[7:0]
Mul reg1, reg2, reg3
Mul reg1, reg2
Mul reg, eaddr
Mula reg,#data[7:0]
Mula reg1, reg2, reg3
Mula reg1, reg2
Mula reg, eaddr
Mshl reg,#shift[2:0]
Mshr reg,#shift[2:0]
Mshra reg,#shift[2:0]
Cmp reg,#data[7:0]
Cmp reg1, reg2
Cmp reg, eaddr
Cmpa reg,#data[7:0]
Cmpa reg1, reg2
Cmpa reg, eaddr
Tstb reg,#bit[2:0]
Setb reg,#bit[2:0]
Clrb reg,#bit[2:0]
Invb reg,#bit[2:0]
© Semtech 2005
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a*
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
-, -, Z, a
-, -, Z, a
-, -, Z, a
-, -, Z, a
a := reg2-1; if a=hFF then C := 0 else C := 1; reg1 := a
a := reg-1; if a=hFF then C := 0 else C := 1; reg := a
a := DM(eaddr)-1; if a=hFF then C := 0 else C := 1; reg := a
a := reg2-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg1 := a
a := reg-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a
a := DM(eaddr)-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a
a := reg and data[7:0]; reg := a
a := reg2 and reg3; reg1 := a
a := reg1 and reg2; reg1 := a
a := reg and DM(eaddr); reg := a
a := reg or data[7:0]; reg := a
a := reg2 or reg3; reg1 := a
a := reg1 or reg2; reg1 := a
a := reg or DM(eaddr); reg := a
a := reg xor data[7:0]; reg := a
a := reg2 xor reg3; reg1 := a
a := reg1 xor reg2; reg1 := a
a := reg or DM(eaddr); reg := a
a := reg+data[7:0]; if overflow then C:=1 else C := 0; reg := a
a := reg2+reg3; if overflow then C:=1 else C := 0; reg1 := a
a := reg1+reg2; if overflow then C:=1 else C := 0; reg1 := a
a := reg+DM(eaddr); if overflow then C:=1 else C := 0; reg := a
a := reg+data[7:0]+C; if overflow then C:=1 else C := 0; reg := a
a := reg2+reg3+C; if overflow then C:=1 else C := 0; reg1 := a
a := reg1+reg2+C; if overflow then C:=1 else C := 0; reg1 := a
a := reg+DM(eaddr)+C; if overflow then C:=1 else C := 0; reg := a
a := data[7:0]-reg; if underflow then C := 0 else C := 1; reg := a
a := reg2-reg3; if underflow then C := 0 else C := 1; reg1 := a
a := reg2-reg1; if underflow then C := 0 else C := 1; reg1 := a
a := DM(eaddr)-reg; if underflow then C := 0 else C := 1; reg := a
a := data[7:0]-reg-(1-C); if underflow then C := 0 else C := 1; reg := a
a := reg2-reg3-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := reg2-reg1-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := DM(eaddr)-reg-(1-C); if underflow then C := 0 else C := 1; reg := a
a := reg-data[7:0]; if underflow then C := 0 else C := 1; reg := a
a := reg3-reg2; if underflow then C := 0 else C := 1; reg1 := a
a := reg1-reg2; if underflow then C := 0 else C := 1; reg1 := a
a := reg-DM(eaddr); if underflow then C := 0 else C := 1; reg := a
a := reg-data[7:0]-(1-C); if underflow then C := 0 else C := 1; reg := a
a := reg3-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := reg1-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := reg-DM(eaddr)-(1-C); if underflow then C := 0 else C := 1; reg := a
a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8]
a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8]
a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8]
a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8]
a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8]
a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8]
a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8]
a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8]
a := (reg*2^shift)[7:0]; reg := (reg*2^shift)[15:8]
a := (reg*2^(8-shift)[7:0]; reg := (reg*2^(8-shift)[15:8]
a := (reg*2^(8-shift)[7:0]; reg := (reg*2^(8-shift)[15:8]
a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a[bit] := reg[bit]; other bits in a are 0
reg[bit] := 1; other bits unchanged; a := reg
reg[bit] := 0; other bits unchanged; a := reg
reg[bit] := not reg[bit]; other bits unchanged; a := reg
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