GS2971A Datasheet, PDF (84/152 Pages) Gennum Corporation – Integrated audio clock generator

WCLK
ACLK
AOUT[8/7:2/1] 23 22 21
MSB
Channel A (Left)
6 5 43 2 10
LSB
Figure 4-39:Serial Audio, Left Justified, MSB First
Channel B (Right)
23 22 21
MSB
65 4 32 10
LSB
WCLK
ACLK
AOUT[8/7:2/1] 0 1 2
LSB
Channel A (Left)
17 18 19 20 21 22 23
MSB
Figure 4-40:Serial Audio, Left Justified, LSB First
Channel B (Right)
0 12
LSB
17 18 19 20 21 22 23
MSB
WCLK
ACLK
AOUT[8/7:2/1]
Channel A (Left)
23 22 21 20 19 18 17
MSB
2 10
LSB
Figure 4-41:Serial Audio, Right Justified, MSB First
Channel B (Right)
23 22 21 20 19 18 17
MSB
21 0
LSB
WCLK
ACLK
AOUT[8/7:2/1]
Channel A (Left)
01 23 45 6
LSB
21 22 23
MSB
Figure 4-42:Serial Audio, Right Justified, LSB First
Channel B (Right)
0 12 3 45 6
LSB
21 22 23
MSB
4.19.2.1 AES/EBU Mode
In AES/EBU output mode, the audio de-embedder uses a 128fs (6.144MHz audio bit
clock) clock as shown in Figure 4-43.
AMCLK
(128fs)
AOUT_1/2, AOUT_3/4
AOUT_5/6, AOUT_7/8
6.144MHz
Figure 4-43:AES/EBU Audio Output to Bit Clock Timing
4.19.2.2 Audio Data Packet Extraction Block
The audio de-embedder looks for audio data packets on every line of the incoming
video.
The audio data must be embedded according to SMPTE 272M (SD) or SMPTE 299M (HD
or 3G).
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
84 of 152