GS2971A Datasheet, PDF (63/152 Pages) Gennum Corporation – Integrated audio clock generator

By default (after power up or after systems reset), the four RASTER_STRUCTURE,
VD_STD, STD_LOCK and INT/PROG registers are set to zero. These registers are also
cleared when the SMPTE_BYPASS pin is LOW.
4.13.1 2K Support
In order to fully support 2K standards without customer intervention, Gennum provides
FPGA code for enhancing the GS2971A's 2K capability.
The features of the 2K FPGA enhancement are:
• Automatic video standard detection for 2K standards
• 1/1.001 rate detection for 2K standards
• CEA-861 timing generation for 2K standards
• Automatic enabling of audio extraction
This enhancement is an interface between the GS2971A and the customer system. The
behaviour of the GS2971A with or without the additional 2K enhancement FPGA code
is identical from a user-perspective.
GS2971A
Level_B
FPGA
GIb_MUX
PLL
÷1
÷2
0
1
GIb_Buf
Pclk_div2
Pclk
GS2971A_GSPI_SDI
Host_GSPI_CS
GS2971A_GSPI_CS
Host_GSPI_SCLK
GS2971A_GSPI_SCLK
Host_GSPI_SDI
GS2971A_GSPI_SDOUT
Host_GSPI_SDOUT
STAT3
Host_GSPI_busy
STAT4
Level_B
STAT5
WO_2K
rate_m_o
clk_27M_ref
std_2K_det_o
reset
dy_out_o[9:0]
smpte_bypass_i
dc_out_o[9:0]
tim_861
fvh_o[2:0]
dy_in_i[9:0]
dc_in_i[9:0]
fvh_i[2:0]
Level_B
Host
Interface
Control
Vid_Out[19:0]
HVF[2:0]
Figure 4-30:2K Feature Enhancement
4.14 Data Format Detection & Indication
In addition to detecting the video standard, the GS2971A detects the data format, i.e.
SDTI, SDI, TDM data (SMPTE 346M), etc.
This information is represented by bits in the DATA_FORMAT_DSX register accessible
through the host interface.
Data format detection is only carried out when the LOCKED signal is HIGH.
By default (at power up or after system reset), the DATA_FORMAT_DSX register is set to
Fh (undefined). This register is also set as undefined when the LOCKED signal is LOW
and/or the SMPTE_BYPASS pin is LOW.
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
63 of 152