GS1582 Datasheet, PDF (55/115 Pages) Gennum Corporation – Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™

0
34
24 -bit
Sync
Preamble
LSB
24-bit Audio Sample Word
27 28 29 30 31
MSB V U C P
0
34
78
20-bit
Sync
Preamble
Aux
Data
LSB
20-bit Audio Sample Word
27 28 29 30 31
MSB V U C P
0
34
78
11 12
16-bit
Sync
Preamble
Aux
Data
Set To
Zero
LSB
16-bit Audio Sample Word
27 28 29 30 31
MSB V U C P
Figure 4-19: AES/EBU Sub-frame Formatting
Validity Bit
User Data Bit
Channel Status Bit
Parity Bit
The audio clock to data timing and input format is shown in Figure 4-20.
AIN 0 1 2 3 4 5 6 7 8
Preamble
AUX
LSB
27 28 29 30 31 0 1 2 3 4 5 6 7 8
MSB V U C P
Preamble
AUX
LSB
Figure 4-20: AES/EBU Audio Input Format
27 28 29 30 31
MSB V U C P
NOTE: Due to the bi-phase mark encoding used in AES/EBU mode, for each logic 1 bit
period, there will be an additional transition. In Figure 4-20, this additional transition is
not shown.
In the event of a parity error in Stereo Pair A in AES/EBU mode, the GS1582 will set the
AES_ERRA bit in the host interface. The same is true of AES_ERRB for Stereo Pair B,
AES_ERRC for Stereo Pair C, and AES_ERRD for Stereo Pair D.
NOTE: In order to read back the parity error bits of register 1, register 2 must be read first
to trigger an update of these bits. The parity error bits will be cleared when read from
register 1.
4.7.17.2 Serial Audio Input Mode
In serial audio input modes, the GS1582 clocks the audio data input on the rising edge of
the ACLK_1/2 input clock at 64fs (3.072MHz), as shown in Figure 4-21, Figure 4-24 and
Figure 4-25 below.
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleaner^TM
Data Sheet
40117 - 4
December 2011
55 of 115