GS2970A Datasheet, PDF (50/150 Pages) Gennum Corporation – Integrated audio clock generator

PC LK
LU M A D A T A IN P U T
C H R O M A D A T A IN P U T
H
V
F
3FF
000
3FF
000
H S IG N A L T IM IN G :
000
000
X Y Z (EAV)
X Y Z (EAV)
H _C O N F IG = LO W
3FF
000
3FF
000
H _C O N F IG = H IG H
000
000
X Y Z (SAV)
X Y Z (SAV)
Figure 4-14:H:V:F Output Timing - HD 20-bit Output Mode
PC LK
M U L T IP LE X E D Y 'C bC r D A T A IN P U T
H
V
F
PC LK
M U L T IP LE X E D Y 'C bC r D A T A IN P U T
H
V
F
3FF
3FF
000
000
000
0 0 0 X Y Z (EAV) X Y Z (EAV)
H V F T IM IN G A T E A V
3FF
3FF
000
000
000
000
X Y Z (SAV) X Y Z (SAV)
H V F T IM IN G A T S A V
Figure 4-15:H:V:F Output Timing - HD 10-bit Output Mode
PCLK
C H R O M A D A T A IN P U T
LU M A D ATA IN P U T
H
V
F
3FF
000
000
X Y Z (EAV)
H S IG N A L T IM IN G :
H _C O N F IG = LO W
3FF
000
000
X Y Z (SAV)
H _C O N F IG = H IG H
Figure 4-16:H:V:F Output Timing - SD 20-bit Output Mode
PC LK
M U L T IP LE X E D Y 'C b C r D A T A IN P U T
H
V
F
3FF
000
H S IG N A L T IM IN G :
000
X Y Z (EAV)
H _C O N F IG = LO W
3FF
000
000
X Y Z (SAV)
H _C O N F IG = H IG H
Figure 4-17:H:V:F Output Timing - SD 10-bit Output Mode
4.12.1 CEA-861 Timing Generation
The GS2970A is capable of generating CEA 861 timing instead of SMPTE HVF timing for
all of the supported video formats.
This mode is selected when the TIM_861 pin is HIGH.
Horizontal sync (HSYNC), Vertical sync (VSYNC), and Data Enable (DE) timing are
output on the STAT[2:0] pins by default.
Table 4-9 shows the CEA-861 formats supported by the GS2970A:
GS2970A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54244 - 2
September 2012
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