SC1486A Datasheet, PDF (14/29 Pages) Semtech Corporation – Dual Synchronous Buck DDR and DDR2 Power Supply Controller

SC1486A
POWER MANAGEMENT
Application Information (Cont.)
Design Procedure (Cont.)
For our DDR2 VDDQ example:
I_{RIPPLE_VIN(MIN)} = 2.07A_P-P and I_{RIPPLE_VIN(MAX)} = 2.73A_P-P
From this we can calculate the minimum inductor
current rating for normal operation:
ERR = 144mV and ERR = 36mV, therefore
TR
DC
R_{ESR_TR(MAX)} = 9.5mΩ for a full 10A load transient
We will select a value of 12.5mΩ maximum for our
design, which would be achieved by using two 25mΩ
output capacitors in parallel.
I = I + ^I ₂ A _{INDUCTOR(MIN)}
OUT ( MAX )
RIPPLE _ VIN(MAX )
(MIN)
For our DDR2 VDDQ example:
I_{INDUCTOR(MIN)} = 11.4A_(MIN)
Note that for constant-on converters there is a minimum
ESR requirement for stability which can be calculated as
follows:
R_ESR(MIN)
=
2•
3
π • C_OUT
•
f_SW
Next we will calculate the maximum output capacitor
equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (R_{ESR_ST(MAX)}) and transient ESR
(R_{ESR_TR(MAX)}):
( ) _{R = ESR _ ST(MAX)}
ERR_ST − ERR_DC
I_{RIPPLE _ VIN(MAX)}
• 2 _Ohms
Where ERR_ST is the static output tolerance and ERR_DC is
the DC error. The DC error will be 1% plus the tolerance
of the feedback resistors, thus 2% total for 1% feed-
back resistors.
For our DDR2 VDDQ example:
ERR_ST = 100mV and ERR_DC = 36mV, therefore
R_{ESR_ST(MAX)} = 47mΩ
( ) _{RESR _ TR(MAX)}
=
ERR_TR − ERR_DC
^IOUT
+
I_{RIPPLE _ VIN(MAX )}
2

Ohms
Where ERR_TR is the transient output tolerance. Note that
this calculation assumes that the worst case load tran-
sient is full load. For half of full load, divide the I_OUT term
by 2.
This criteria should be checked once the output
capacitance has been determined.
Now that we know the output ESR we can calculate the
output ripple voltage:
V = R • I V _{RIPPLE _ VIN(MAX)}
ESR RIPPLE _ VIN(MAX) P−P
and
V = R • I V _{RIPPLE _ VIN(MIN)}
ESR RIPPLE _ VIN(MIN) P−P
For our DDR2 VDDQ example:
V_{RIPPLE_VIN(MAX)} = 34mV_P-P and V_{RIPPLE_VIN(MIN)} = 26mV_P-P
Note that in order for the device to regulate in a
controlled manner, the ripple content at the feedback
pin, V_FB, should be approximately 15mV_P-P at minimum
V , and worst case no smaller than 10mV . If
IN
P-P
V
is less than 15mV the above component
RIPPLE_VIN(MIN)
P-P
values should be revisited in order to improve this. Quite
often a small capacitor, C_TOP, is required in parallel with
the top feedback resistor, R , in order to ensure that
TOP
V is large enough. C should not be greater than
FB
TOP
100pF. The value of C_TOP can be calculated as follows,
where R_BOT is the bottom feedback resistor. Firstly
calculating the value of Z required:
TOP
( ) Z_TOP
=
R_BOT
0.015
•
V_{RIPPLE _ VIN(MIN)}
− 0.015
Ohms
For our DDR2 VDDQ example:
 2004 Semtech Corp.
Secondly calculating the value of C_TOP required to achieve
this:
14
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