SC1486A Datasheet, PDF (13/29 Pages) Semtech Corporation – Dual Synchronous Buck DDR and DDR2 Power Supply Controller

SC1486A
POWER MANAGEMENT
Application Information (Cont.)
Design Procedure
Prior to designing an output and making component
selections, it is necessary to determine the input voltage
range and the output voltage specifications. For purposes
of demonstrating the procedure the VDDQ output for the
schematic on page 17 will be designed.
The maximum input voltage (V_IN(MAX)) is determined by the
highest AC adaptor voltage. The minimum input voltage
(V_IN(MIN)) is determined by the lowest battery voltage after
accounting for voltage drops due to connectors, fuses
and battery selector switches. For the purposes of this
design example we will use a V range of 7.5V to 20.5V.
IN
Four parameters are needed for the output:
1) nominal output voltage, V_OUT (for DDR2 this is 1.8V)
2) static (or DC) tolerance, TOL (for DDR2 this is
ST
+/-0.1V)
3) transient tolerance, TOL_TR and size of transient (for
DDR2 this is undefined, so assume +/-8% for purposes
of this demonstration).
4) maximum output current, I_OUT (we will design for 10A)
Switching frequency determines the trade-off between
size and efficiency. Increased frequency increases the
switching losses in the MOSFETs, since losses are a
function of VIN². Knowing the maximum input voltage and
budget for MOSFET switches usually dictates where the
design ends up. It is recommended that the two outputs
are designed to operate at frequencies approximately
25% apart to avoid any possible interaction. It is also
recommended that the higher frequency output is the
lower output voltage output, since this will tend to have
lower output ripple and tighter specifications. The
default R_tON values of 1MΩ and 649kΩ are suggested
as a starting point, but these are not set in stone. The
first thing to do is to calculate the on-time, t , at V
ON
IN(MIN)
and V_IN(MAX), since this depends only upon V_IN, V_OUT and
R_tON. For V_OUT < 3.3V:
( ) tON_ VIN(MIN) = 3.3 • 10−12 • RtON + 37 • 103

•
V_OUT
V_IN(MIN)



+
50
• 10^−9 s
( ) ^{f = SW _ VIN(MIN)}
V_OUT
V • t _{IN(MIN) ON _ VIN(MIN)}
Hz
and
( ) ^{f = SW _ VIN(MAX)}
V_OUT
V • t _{IN(MAX) ON _ VIN(MAX)}
Hz
t_ON is generated by a one-shot comparator that samples
V_IN via R_tON, converting this to a current. This current is
used to charge an internal 3.3pF capacitor to V_OUT. The
equations above reflect this along with any internal com-
ponents or delays that influence t_ON. For our DDR2 VDDQ
example we select R_tON = 1MΩ:
t_{ON_VIN(MIN)} = 871ns and t_{ON_VIN(MAX)} = 350ns
f_{SW_VIN(MIN)} = 275kHz and f_{SW_VIN(MAX)} = 251kHz
Now that we know t_ON we can calculate suitable values
for the inductor. To do this we select an acceptable
inductor ripple current. The calculations below assume
50% of I_OUT which will give us a starting place.
( ) _{( )} L = _VIN(MIN)
V − V _IN(MIN)
OUT
•
t _{ON _ VIN(MIN)}
0.5 • I_OUT
H
and
( ) _{( )} L = _VIN(MAX)
V − V _IN(MAX)
OUT
•
t _{ON _ VIN(MAX )}
0.5 • I_OUT
H
For our DDR2 VDDQ example:
L_VIN(MIN) = 1µH and L_VIN(MAX) = 1.3µH
We will select an inductor value of 2.4µH to reduce the
ripple current, which can be calculated as follows:
I = (V − V )• ^t _L A _{RIPPLE _ VIN(MIN)}
IN(MIN)
OUT
ON _ VIN(MIN)
P−P
and
and
( ) tON_ VIN(MAX) = 3.3 • 10−12 • RtON + 37 • 103

•
V_OUT
V_IN(MAX)



+
50
• 10^−9 s
From these values of t_ON we can calculate the nominal
switching frequency as follows:
I = (V − V )• ^t _L A _{RIPPLE _ VIN(MAX)}
IN(MAX )
OUT
ON _ VIN(MAX )
P−P
 2004 Semtech Corp.
13
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