UR6HCPS2-SP40 Datasheet, PDF (13/22 Pages) Semtech Corporation – Converts PS/2 Data to Serial or SPI

SERIAL PERIPHERAL INTERFACE (SPI) MODE
The Serial Peripheral Interface (SPI) is a synchronous bi-directional multi-slave protocol. In SPI mode, the
PS2Adapt^TM acts as a slave device. The IC only supports transmission and doesn't support receiving. SPI data
transfer can be performed at a maximum clock rate of 500 KHz. If CONF0 pin is high, the data transfer sequence is
MSB to LSB; if CONF0 pin is low the sequence is LSB to MSB. The SDATA pin outputs data every time the transfer
clock changes from high to low level.
Protocol:
1. The UR6HCPS2-SP40 asserts _ATN low to indicate that a mouse packet is waiting for transfer.
2. The Host asserts _SS low to indicate that it is ready to receive data. _SS low means the system selected SPI
PS2Adapt^TM as its communication device.
3. On detecting _SS low, the IC enables the SPI interface and places data in the SPI data TX buffer. After a short
delay, the system supplies eight clocks to get the data from the IC. The minimum time t2 from _SS low to first SPI
clock is 50us.
4. When a byte is transferred successfully, the system has to wait a minimum of 50us to begin the clocks for next
byte transmission.
5. When the four-byte mouse package / 2-byte keyboard package is transmitted, the system stops the SPI clock. If
it needs to communicate with other SPI devices, it has to wait for _ATN return to high. _ATN high means the SPI port
of UR6HCPS2-SP40 is now in high Impedance State.
_ATN
_SS
SCLK
SDATA
1st 2nd
Byte Byte
t1
t2
t3
Last
Byte
t4
Figure 2: SPI Transmission Timing: (_SS toggles for every package).
Notes on the Protocol:
To assure the fast transmission, system must assert _SS low as soon as possible, see Figure 2. If the system is
ready to get data, it doesn't have to raise _SS between packages, see Figure 3.
Copyright Semtech, 2002-2001
13
DOC6-PS2-SP40-DS-102
www.semtech.com